HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 220
HD6413003TF16V
Manufacturer Part Number
HD6413003TF16V
Description
MCU 5V 0K PB-FREE 112-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13003TF16V.pdf
(717 pages)
Specifications of HD6413003TF16V
Core Size
16-Bit
Oscillator Type
Internal
Core Processor
H8/300H
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
No. Of I/o's
58
Ram Memory Size
512Byte
Cpu Speed
16MHz
No. Of Timers
11
No. Of Pwm Channels
4
Digital Ic Case Style
QFP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/300H
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Quantity
Price
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Part Number:
HD6413003TF16V
Manufacturer:
ITT
Quantity:
12 000
Company:
Part Number:
HD6413003TF16V
Manufacturer:
RENESAS
Quantity:
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Part Number:
HD6413003TF16V
Manufacturer:
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Figure 8-3 shows a sample setup procedure for I/O mode.
8.4.3 Idle Mode
Idle mode can be selected independently for each channel.
One byte or word is transferred at each transfer request in idle mode. A designated number of
these transfers are executed. One address is specified in the memory address register (MAR), the
other in the I/O address register (IOAR). The direction of transfer is determined automatically
from the activation source. The transfer is from the address specified in IOAR to the address
specified in MAR if activated by an SCI receive-data-full interrupt, and from the address specified
in MAR to the address specified in IOAR otherwise.
Table 8-7 indicates the register functions in idle mode.
destination addresses
Set transfer count
Set source and
Read DTCR
Set DTCR
I/O mode
I/O
Figure 8-3 I/O Mode Setup Procedure (Example)
1
2
3
4
1.
2.
3.
4.
200
Set the source and destination addresses
in MAR and IOAR. The transfer direction is
determined automatically from the activation
source.
Set the transfer count in ETCR.
Read DTCR while the DTE bit is cleared to 0.
Set the DTCR bits as follows.
•
•
•
•
•
•
Select the DMAC activation source with bits
DTS2 to DTS0.
Set or clear the DTIE bit to enable or disable
the CPU interrupt at the end of the transfer.
Clear the RPE bit to 0 to select I/O mode.
Select MAR increment or decrement with the
DTID bit.
Select byte size or word size with the DTSZ bit.
Set the DTE bit to 1 to enable the transfer.
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