HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 275
HD6413003TF16V
Manufacturer Part Number
HD6413003TF16V
Description
MCU 5V 0K PB-FREE 112-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13003TF16V.pdf
(717 pages)
Specifications of HD6413003TF16V
Core Size
16-Bit
Oscillator Type
Internal
Core Processor
H8/300H
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
No. Of I/o's
58
Ram Memory Size
512Byte
Cpu Speed
16MHz
No. Of Timers
11
No. Of Pwm Channels
4
Digital Ic Case Style
QFP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/300H
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6413003TF16V
Manufacturer:
ITT
Quantity:
12 000
Company:
Part Number:
HD6413003TF16V
Manufacturer:
RENESAS
Quantity:
36
Part Number:
HD6413003TF16V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Port 8 Data Direction Register (P8DDR): P8DDR is an 8-bit write-only register that can select
input or output for each pin in port 8.
When bits in P8DDR bit are set to 1, P8
a generic output pin. When bits in P8DDR are cleared to 0, the corresponding pins become input
pins.
P8DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P8DDR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting, so if a P8DDR bit is set to 1, the corresponding pin maintains its
output state in software standby mode.
Port 8 Data Register (P8DR): P8DR is an 8-bit readable/writable register that stores data for pins
P8
When a bit in P8DDR is set to 1, if port 8 is read the value of the corresponding P8DR bit is
returned directly. When a bit in P8DDR is cleared to 0, if port 8 is read the corresponding pin level
is read.
Bits 7 to 5 are reserved. They cannot be modified and always read 1.
P8DR is initialized to H'E0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
4
to P8
0
.
—
—
—
—
7
1
7
1
Reserved bits
Reserved bits
—
—
—
—
6
1
6
1
4
—
—
—
—
5
1
5
1
to P8
1
P8 DDR
255
become CS
R/W
P8
4
W
4
1
4
0
4
P8 DDR
Port 8 data direction 4 to 0
These bits select input or
output for port 8 pins
R/W
P8
0
3
W
3
0
3
0
to CS
Port 8 data 4 to 0
These bits store data
for port 8 pins
3
P8 DDR
3
output pins and P8
R/W
P8
2
W
2
0
2
0
2
P8 DDR
R/W
P8
1
W
1
0
1
0
1
P8 DDR
0
becomes
R/W
P8
0
W
0
0
0
0
0
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