HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 242
HD6413003TF16V
Manufacturer Part Number
HD6413003TF16V
Description
MCU 5V 0K PB-FREE 112-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13003TF16V.pdf
(717 pages)
Specifications of HD6413003TF16V
Core Size
16-Bit
Oscillator Type
Internal
Core Processor
H8/300H
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
No. Of I/o's
58
Ram Memory Size
512Byte
Cpu Speed
16MHz
No. Of Timers
11
No. Of Pwm Channels
4
Digital Ic Case Style
QFP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/300H
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6413003TF16V
Manufacturer:
ITT
Quantity:
12 000
Company:
Part Number:
HD6413003TF16V
Manufacturer:
RENESAS
Quantity:
36
Part Number:
HD6413003TF16V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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8.4.9 Multiple-Channel Operation
The DMAC channel priority order is: channel 0 > channel 1 > channel 2 > channel 3, and
channel A > channel B. Table 8-12 shows the complete priority order. Group 0 and group 1
operate as two independent bus masters.
Table 8-12 Channel Priority Order
Bus Master
Group 0
Group 1
Multiple-Channel Operation in the Same Group: If transfers are requested on two or more
channels simultaneously in the same group, or if a transfer on one channel is requested during a
transfer on another channel in the same group, the DMAC operates as follows.
•
•
•
•
When a transfer is requested, the DMAC requests the bus right. When it gets the bus right, it
starts a transfer on the highest-priority channel at that time.
Once a transfer starts on one channel, requests to other channels in the same group are held
pending until that channel releases the bus.
After each transfer in short address mode, and each externally-requested or cycle-steal
transfer in normal mode, the DMAC releases the bus and returns to step 1. After releasing the
bus, if there is a transfer request for another channel in the same group, the DMAC requests
the bus again.
After completion of a burst-mode transfer, or after transfer of one block in block transfer
mode, the DMAC releases the bus and returns to step 1. If there is a transfer request for a
higher-priority channel or a bus request from a higher-priority bus master, however, the
DMAC releases the bus after completing the transfer of the current byte or word. After
releasing the bus, if there is a transfer request for another channel in the same group, the
DMAC requests the bus again.
Short Address Mode
Channel 0A
Channel 0B
Channel 1A
Channel 1B
Channel 2A
Channel 2B
Channel 3A
Channel 3B
Full Address Mode
Channel 0
Channel 1
Channel 2
Channel 3
222
Priority
High
Low
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