HD6413003TF16V Renesas Electronics America, HD6413003TF16V Datasheet - Page 284
HD6413003TF16V
Manufacturer Part Number
HD6413003TF16V
Description
MCU 5V 0K PB-FREE 112-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13003TF16V.pdf
(717 pages)
Specifications of HD6413003TF16V
Core Size
16-Bit
Oscillator Type
Internal
Core Processor
H8/300H
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
No. Of I/o's
58
Ram Memory Size
512Byte
Cpu Speed
16MHz
No. Of Timers
11
No. Of Pwm Channels
4
Digital Ic Case Style
QFP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/300H
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6413003TF16V
Manufacturer:
ITT
Quantity:
12 000
Company:
Part Number:
HD6413003TF16V
Manufacturer:
RENESAS
Quantity:
36
Part Number:
HD6413003TF16V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Table 9-14 Port A Pin Functions (cont)
Pin
PA
PA
6
5
/TP
/TP
6
5
/TIOCA
/TIOCB
2
1
Pin Functions and Selection Method
ITU channel 2 settings (bit PWM2 in TMDR and bits IOA2 to IOA0 in TIOR2),
bit NDER6 in NDERA, and bit PA
follows
Note: * TIOCA
ITU channel 1 settings (bit PWM1 in TMDR and bits IOB2 to IOB0 in TIOR1),
bit NDER5 in NDERA, and bit PA
follows
Note: * TIOCB
ITU channel
2 settings
PA
NDER6
Pin function
ITU channel
2 settings
PWM2
IOA2
IOA1
IOA0
ITU channel
2 settings
PA
NDER5
Pin function
ITU channel
1 settings
IOB2
IOB1
IOB0
6
5
DDR
DDR
2
1
input when IOA2 = 1.
input when IOB2 = 1 and PWM1 = 0.
2
0
0
2
0
0
1 in table below
1 in table below
TIOCA
TIOCB
264
—
—
—
—
0
0
1
0
2
1
6
5
output
output
DDR in PADDR select the pin function as
DDR in PADDR select the pin function as
0
1
1
0
1
—
1
—
1
input
input
PA
PA
—
—
—
—
2
0
1
0
6
5
2 in table below
2 in table below
TIOCA
TIOCB
output
output
PA
PA
—
—
2
1
0
1
0
1
2
1
6
5
input*
input*
—
—
—
1
1
output
output
TP
TP
1
1
1
1
6
5
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