HD64F2633RTE28 Renesas Electronics America, HD64F2633RTE28 Datasheet - Page 147

IC H8S MCU FLASH 256K 120-TQFP

HD64F2633RTE28

Manufacturer Part Number
HD64F2633RTE28
Description
IC H8S MCU FLASH 256K 120-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of HD64F2633RTE28

Core Processor
H8S/2600
Core Size
16-Bit
Speed
28MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
73
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
2.2.38
MAC (Multiply and ACcumulate)
Operation
(EAn)
MAC register
ERn
ERm + 2
Assembly-Language Format
MAC @ERn+, @ERm+
Operand Size
Description
This instruction performs signed multiplication on two 16-bit operands at addresses given by the
contents of general registers ERn and ERm, adds the 32-bit product to the contents of the MAC
register, and stores the sum in the MAC register. After this operation, ERn and ERm are both
incremented by 2.
The operation can be carried out in saturating or non-saturating mode, depending on the MACS
bit in a system control register. (SYSCR)
See the relevant hardware manual for further information.
In non-saturating mode, MACH and MACL are concatenated to store a 42-bit result. The value of
bit 41 is copied into the upper 22 bits of MACH as a sign extension.
In saturating mode, only MACL is valid, and the result is limited to the range from H'80000000
(minimum value) to H'7FFFFFFF (maximum value). If the result overflows in the negative
direction, H'80000000 (the minimum value) is stored in MACL. If the result overflows in the
positive direction, H'7FFFFFFF (the maximum value) is stored in MACL. The LSB of the MACH
register indicates the status of the overflow flag (V-MULT) in the multiplier. Other bits retain
their previous contents.
This instruction is supported only by the H8S/2600 CPU.
+ 2
(EAm) + MAC register
MAC
ERn
ERm
Condition Code
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Rev. 4.00 Feb 24, 2006 page 131 of 322
I
UI H
Section 2 Instruction Descriptions
Multiply and Accumulate
U
—*
N
REJ09B0139-0400
—*
Z
—* —
V
C

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