HD64F2633RTE28 Renesas Electronics America, HD64F2633RTE28 Datasheet - Page 327

IC H8S MCU FLASH 256K 120-TQFP

HD64F2633RTE28

Manufacturer Part Number
HD64F2633RTE28
Description
IC H8S MCU FLASH 256K 120-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of HD64F2633RTE28

Core Processor
H8S/2600
Core Size
16-Bit
Speed
28MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
73
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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3.3
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address
(vector) from the exception vector table and branches to that address.
3.3.1
Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 3.1
indicates the types of exception handling and their priority. Trap instruction exception handling is
always accepted, in the program execution state.
Exception handling and the stack structure differ according to the interrupt control mode set in
SYSCR.
Table 3.1
Priority
High
Low
Notes: 1. Traces are enabled only in interrupt control modes 2 and 3. Trace exception-handling is
For details on interrupt control modes, exception sources, and exception handling, refer to the
relevant microcontroller hardware manual.
2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,
3. Trap instruction exception handling is always accepted, in the program execution state.
Types of Exception Handling and Their Priority
Exception-Handling State
Type of Exception
Reset
Trace
Interrupt
Trap instruction
not executed at the end of the RTE instruction.
or immediately after reset exception handling.
Exception Handling Types and Priority
Detection Timing
When TRAPA instruction
Synchronized with clock
End of instruction
execution or end of
exception-handling
sequence *
End of instruction
execution or end of
exception-handling
sequence *
is executed
1
2
Rev. 4.00 Feb 24, 2006 page 311 of 322
Start of Exception Handling
Exception handling starts
immediately when RES changes
from low to high
When the trace (T) bit is set to 1, the
trace starts at the end of the current
instruction or current exception-
handling sequence
When an interrupt is requested,
exception handling starts at the end
of the current instruction or current
exception-handling sequence
Exception handling starts when a
trap (TRAPA) instruction is
executed *
Section 3 Processing States
3
REJ09B0139-0400