HD64F2633RTE28 Renesas Electronics America, HD64F2633RTE28 Datasheet - Page 224

IC H8S MCU FLASH 256K 120-TQFP

HD64F2633RTE28

Manufacturer Part Number
HD64F2633RTE28
Description
IC H8S MCU FLASH 256K 120-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of HD64F2633RTE28

Core Processor
H8S/2600
Core Size
16-Bit
Speed
28MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
73
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Section 2 Instruction Descriptions
2.2.58 (5)
SHAR (SHift Arithmetic Right)
Operation
ERd (right arithmetic shift)
Assembly-Language Format
SHAR.L ERd
Operand Size
Longword
Description
This instruction shifts the bits in a 32-bit register ERd (destination operand) one bit to the right.
Bit 0 shifts into the carry flag. Bit 31 shifts into itself. Since bit 31 remains unaltered, the sign
does not change.
Available Registers
ERd: ER0 to ER7
Operand Format and Number of States Required for Execution
Notes
Rev. 4.00 Feb 24, 2006 page 208 of 322
REJ09B0139-0400
Register direct
Addressing
Mode
SHAR (L)
Mnemonic
SHAR.L
MSB
b31
Operands
ERd
ERd
. . . . . .
1st byte
1
1
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Always cleared to 0.
C: Receives the previous value in bit 0.
2nd byte
B
Instruction Format
cleared to 0.
cleared to 0.
I
0 erd
UI H
LSB
b0
3rd byte
U
C
N
4th byte
Shift Arithmetic
Z
V
0
States
No. of
C
1

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