HD64F2633RTE28 Renesas Electronics America, HD64F2633RTE28 Datasheet - Page 217

• Manufacturer Part Number: HD64F2633RTE28
• Description: IC H8S MCU FLASH 256K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2633RTE28

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 28MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 73
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

2.2.57 (4)
SHAL (SHift Arithmetic Left)
Operation
Rd (left arithmetic shift)
Assembly-Language Format
SHAL.W #2, Rd
Operand Size
Word
Description
This instruction shifts the bits in a 16-bit register Rd (destination operand) two bits to the left. Bit
14 shifts into the carry flag. Bits 0 and 1 are cleared to 0.
Available Registers
Rd: R0 to R7, E0 to E7
Operand Format and Number of States Required for Execution
Notes
The SHAL instruction differs from the SHLL instruction in its effect on the overflow flag.
Register direct
Addressing
Mode
SHAL (W)
Mnemonic
SHAL.W
C
Rd
MSB
Operands
b15
#2, Rd
b14
. . . . . .
1st byte
1
0
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Set to 1 if an overflow occurs; otherwise
C: Receives the previous value in bit 14.
2nd byte
D
Instruction Format
cleared to 0.
cleared to 0.
cleared to 0.
Rev. 4.00 Feb 24, 2006 page 201 of 322
—
I
rd
UI H
—
b1
0
Section 2 Instruction Descriptions
—
3rd byte
LSB
b0
0
—
U
N
0
4th byte
REJ09B0139-0400
Shift Arithmetic
Z
V
States
No. of
C
1