HD64F2633RTE28 Renesas Electronics America, HD64F2633RTE28 Datasheet - Page 41

IC H8S MCU FLASH 256K 120-TQFP

HD64F2633RTE28

Manufacturer Part Number
HD64F2633RTE28
Description
IC H8S MCU FLASH 256K 120-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of HD64F2633RTE28

Core Processor
H8S/2600
Core Size
16-Bit
Speed
28MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
73
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2633RTE28V
Manufacturer:
RENESAS
Quantity:
296
Part Number:
HD64F2633RTE28V
Manufacturer:
RENESAS
Quantity:
784
Type
Arithmetic
operations
Instruction
CMP
NEG
EXTU
EXTS
TAS
MAC
CLRMAC
LDMAC
STMAC
Size *
B/W/L
B/W/L
W/L
W/L
B
L
1
Function
Rd – Rs, Rd – #IMM
Compares data in a general register with data in
another general register or with immediate data, and
sets CCR bits according to the result.
0 – Rd
Takes the two’s complement (arithmetic complement)
of data in a general register.
Rd (zero extension)
Extends the lower 8 bits of a 16-bit register to word
size, or the lower 16 bits of a 32-bit register to longword
size, by padding with zeros on the left.
Rd (sign extension)
Extends the lower 8 bits of a 16-bit register to word
size, or the lower 16 bits of a 32-bit register to longword
size, by extending the sign bit.
@ERd – 0, 1
Tests memory contents, and sets the most significant
bit (bit 7) to 1.
(EAs)
Performs signed multiplication on memory contents
and adds the result to the multiply-accumulate register.
The following operations can be performed:
16 bits
16 bits
Supported by H8S/2600 CPU only.
0
Clears the multiply-accumulate register to zero.
Supported by H8S/2600 CPU only.
Rs
Transfers data between a general register and the
multiply-accumulate register.
Supported by H8S/2600 CPU only.
MAC
MAC, MAC
(EAd) + MAC
16 bits +32 bits
16 bits + 42 bits
Rd
Rev. 4.00 Feb 24, 2006 page 25 of 322
(<bit 7> of @ERd) *
Rd
Rd
Rd
MAC
32 bits, saturating
42 bits, non-saturating
2
REJ09B0139-0400
Section 1 CPU