HD64F2633RTE28 Renesas Electronics America, HD64F2633RTE28 Datasheet - Page 17

IC H8S MCU FLASH 256K 120-TQFP

HD64F2633RTE28

Manufacturer Part Number
HD64F2633RTE28
Description
IC H8S MCU FLASH 256K 120-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of HD64F2633RTE28

Core Processor
H8S/2600
Core Size
16-Bit
Speed
28MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
73
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2633RTE28V
Manufacturer:
RENESAS
Quantity:
296
Part Number:
HD64F2633RTE28V
Manufacturer:
RENESAS
Quantity:
784
1.1
The H8S/2600 CPU and the H8S/2000 CPU are high-speed central processing units with a
common an internal 32-bit architecture. Each CPU is upward-compatible with the H8/300 and
H8/300H CPUs. The H8S/2600 CPU and H8S/2000 CPU have sixteen 16-bit general registers,
can address a 4-Gbyte linear address space, and are ideal for realtime control.
1.1.1
The H8S/2600 CPU and H8S/2000 CPU have the following features.
Upward-compatible with H8/300 and H8/300H CPUs
General-register architecture
Sixty-nine basic instructions (H8S/2000 CPU has sixty-five)
Eight addressing modes
4-Gbyte address space
Can execute H8/300 and H8/300H object programs
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit
registers)
8/16/32-bit arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
Multiply-and-accumulate instruction (H8S/2600 CPU only)
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]
Program: 16 Mbytes
Data:
Features
Overview
4 Gbytes
Section 1 CPU
Rev. 4.00 Feb 24, 2006 page 1 of 322
REJ09B0139-0400
Section 1 CPU