HD64F2633RTE28 Renesas Electronics America, HD64F2633RTE28 Datasheet - Page 57

IC H8S MCU FLASH 256K 120-TQFP

HD64F2633RTE28

Manufacturer Part Number
HD64F2633RTE28
Description
IC H8S MCU FLASH 256K 120-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of HD64F2633RTE28

Core Processor
H8S/2600
Core Size
16-Bit
Speed
28MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
73
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2633RTE28V
Manufacturer:
RENESAS
Quantity:
296
Part Number:
HD64F2633RTE28V
Manufacturer:
RENESAS
Quantity:
784
2.1
This section explains how to read the tables in section 2.2, describing each instruction. Note that
the descriptions of some instructions extend over more than one page.
[1] Mnemonic (Full Name): Gives the full and mnemonic names of the instruction.
[2] Type: Indicates the type of instruction.
[3] Operation: Describes the instruction in symbolic notation. (See section 2.1.2, Operation.)
[4] Assembly-Language Format: Indicates the assembly-language format of the instruction.
[5] Operand Size: Indicates the available operand sizes.
[6] Condition Code: Indicates the effect of instruction execution on the flag bits in the CCR.
[7] Description: Describes the operation of the instruction in detail.
[8] Available Registers: Indicates which registers can be specified in the register field of the
[9] Operand Format and Number of States Required for Execution: Shows the addressing
[10] Notes: Gives notes concerning execution of the instruction.
(See section 2.1.1, Assembler Format.)
(See section 2.1.3, Condition Code.)
instruction.
modes and instruction format together with the number of states required for execution.
Tables and Symbols
[1] Mnemonic (Full Name)
[3] Operation
[4] Assembly-Language Format
[5] Operand Size
[7] Description
[8] Available Registers
[9] Operand Format and Number of States Required for Execution
[10] Notes
Section 2 Instruction Descriptions
[6] Condition Code
Rev. 4.00 Feb 24, 2006 page 41 of 322
Section 2 Instruction Descriptions
[2] Type
REJ09B0139-0400