HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 230

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 4 Caches
• When MMU is off
Rev.7.00 Oct. 10, 2008 Page 144 of 1074
REJ09B0366-0700
When a prefetch instruction is issued for the SQ area, address translation is performed and
external memory address bits [28:10] are generated in accordance with the SZ bit specification.
For external memory address bits [9:5], the address prior to address translation is generated in
the same way as when the MMU is off. External memory address bits [4:0] are fixed at 0.
Transfer from the SQs to external memory is performed to this address.
The SQ area (H'E000 0000 to H'E3FF FFFF) is specified as the address to issue a PREF
instruction. The meaning of address bits [31:0] is as follows:
[31:26]:
[25:6]:
[5]:
[4:2]:
[1:0]
External memory address bits [28:26], which cannot be generated from the above address, are
generated from the QACR0/1 registers.
QACR0 [4:2]:
QACR1 [4:2]:
External memory address bits [4:0] are always fixed at 0 since burst transfer starts at a 32-byte
boundary. In the SH7750, data transfer to a PCMCIA interface area cannot be performed using
an SQ. In the SH7750S or SH7750R, data transfer to a PCMCIA interface area is always
performed using the SA and TC bits in the PTEA register.
111000
Address
0/1
Don't care
00
External memory address bits [28:26] corresponding to SQ0
External memory address bits [28:26] corresponding to SQ1
Store queue specification
External memory address bits [25:6]
0: SQ0 specification
1: SQ1 specification and external memory address bit [5]
No meaning in a prefetch
Fixed at 0