HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 654

MPU 1.5/3.3V 0K I-TEMP PB-FREE 2

HD6417750RF200DV

Manufacturer Part Number
HD6417750RF200DV
Description
MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF200DV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.35 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750RF200DV
Manufacturer:
FREESCALE
Quantity:
450
Section 14 Direct Memory Access Controller (DMAC)
Rev.7.00 Oct. 10, 2008 Page 568 of 1074
REJ09B0366-0700
Notes: 1. In auto-request mode, transfer begins when the NMIF, AE, and TE bits are all 0, and the DE
DMATCR - 1 → DMATCR
Transfer (1 transfer unit)
DMTE interrupt request
(SAR, DAR, DMATCR,
Illegal address check
NMIF, AE, TE = 0?
AE = 1 or DE = 0 or
(reflected in AE bit)
Update SAR, DAR
CHCR, DMAOR)
request issued?
DE, DME = 1?
2. DREQ level detection (external request) in burst mode, or cycle steal mode.
3. DREQ edge detection (external request) in burst mode, or auto-request mode in burst mode.
4. An illegal address is detected by comparing bits TS2–TS0 in CHCRn with SARn and DARn.
DMATCR = 0?
End of transfer
Initial settings
(when IE = 1)
DME = 0?
Yes
Yes
Yes
Yes
Yes
Transfer
NMIF or
and DME bits are set to 1.
Start
*1
Figure 14.2 DMAC Transfer Flowchart
No
No
No
No
No
*4
Normal end
Transfer suspended
AE = 1 or DE = 0 or
DME = 0?
Yes
NMIF or
*3
transfer request mode,
DREQ detection
No
Bus mode,
method
*2

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