HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 315

MPU 1.5/3.3V 0K I-TEMP PB-FREE 2

HD6417750RF200DV

Manufacturer Part Number
HD6417750RF200DV
Description
MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF200DV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.35 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750RF200DV
Manufacturer:
FREESCALE
Quantity:
450
Workarounds: To prevent the problem, use either of workarounds a. or b. below.
a. Include a NOP instruction in the eight words of data following each TRAPA instruction,
b. Include an OR R0,R0 instruction in the five words of data following each TRAPA instruction,
SLEEP instruction, or undefined instruction code H'FFFD.
SLEEP instruction, or undefined instruction code H'FFFD. This workaround also applies to
cases where “the eight words of data following the … instruction … contain H'Fxxx,” as
mentioned in condition 4. b., because two OR instructions are never executed simultaneously,
so a minimum of 5xIck is required for execution.
executed in 4xIck. The maximum number of instructions that can be executed in 2xIck or
4xIck is four or eight, respectively. Therefore, the affected codes are those occurring in
“the four words (or eight words) of data following the instruction.”
Rev.7.00 Oct. 10, 2008 Page 229 of 1074
Section 7 Instruction Set
REJ09B0366-0700

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