HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 778

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 15 Serial Communication Interface (SCI)
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes
2. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts
3. The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is
Figure 15.9 shows an example of the operation for transmission in asynchronous mode.
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that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1.
transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is
generated.
The serial transmit data is sent from the TxD pin in the following order.
a. Start bit: One 0-bit is output.
b. Transmit data: 8-bit or 7-bit data is output in LSB-first order.
c. Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor
d. Stop bit(s): One or two 1-bits (stop bits) are output.
e. Mark state: 1 is output continuously until the start bit that starts the next transmission is
cleared to 0, data is transferred from SCTDR1 to SCTSR1, the stop bit is sent, and then serial
transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SCSSR1 is set to 1, the stop bit is sent, and then
the line goes to the mark state in which 1 is output continuously. If the TEIE bit in SCSCR1 is
set to 1 at this time, a TEI interrupt request is generated.
bit is output. (A format in which neither a parity bit nor a multiprocessor bit is output can
also be selected.)
sent.