HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 488

MPU 1.5/3.3V 0K I-TEMP PB-FREE 2

HD6417750RF200DV

Manufacturer Part Number
HD6417750RF200DV
Description
MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF200DV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.35 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750RF200DV
Manufacturer:
FREESCALE
Quantity:
450
Section 13 Bus State Controller (BSC)
Bit 31—RAS Down (RASD): Sets RAS down mode. When DRAM/RAS down mode is used, set
BE to 1. Do not set RAS down mode in slave mode or partial-sharing mode, or when areas 2 and 3
are both designated as synchronous DRAM interface. See Connecting a 128-Mbit/256-Mbit
Synchronous DRAM with 64-bit Bus Width (SH7750R Only): in section 13.3.5, Synchronous
DRAM Interface.
Bit 31: RASD
0
1
Note: When synchronous DRAM is used in RAS down mode, set bits DMAIW2–DMAIW0 to 000
Bit 30—Mode Register Set (MRSET): Set when a synchronous DRAM mode register setting is
used. See Power-On Sequence in section 13.3.5, Synchronous DRAM Interface.
Bit 30: MRSET
0
1
Bits 29 to 27—RAS Precharge Time at End of Refresh (TRC2–TRC0)
(Synchronous DRAM: auto- and self-refresh both enabled; DRAM: auto- and self-refresh both
enabled)
Note: For setting values and the period during which no command is issued, see 22.3.3, Bus
Bit 29: TRC2
0
1
Rev.7.00 Oct. 10, 2008 Page 402 of 1074
REJ09B0366-0700
and bits A3IW2–A3IW0 to 000.
Timing.
Bit 28: TRC1
0
1
0
1
Description
Auto-precharge mode
RAS down mode
Description
All-bank precharge
Mode register setting
Bit 27: TRC0
0
1
0
1
0
1
0
1
RAS Precharge Interval
Immediately after Refresh
0
3
6
9
12
15
18
21
(Initial value)
(Initial value)
(Initial value)

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