HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 244
HD6417750RF200DV
Manufacturer Part Number
HD6417750RF200DV
Description
MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417750RBP240DV.pdf
(1164 pages)
Specifications of HD6417750RF200DV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.35 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417750RF200DV
Manufacturer:
FREESCALE
Quantity:
450
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Section 5 Exceptions
5.5.3
When the BL bit in SR is 0, general exception and interrupts are accepted.
When the BL bit in SR is 1 and a general exception other than a user break is generated, the CPU's
internal registers and the registers of the other modules are set to their states following a manual
reset, and the CPU branches to the same address as in a reset (H'A000 0000). For the operation in
the event of a user break, see section 20, User Break Controller (UBC).
If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after the BL
bit has been cleared to 0 by software. If a nonmaskable interrupt (NMI) occurs, it can be held
pending or accepted according to the setting made by software.
Thus, normally, SPC and SSR are saved and then the BL bit in SR is cleared to 0, to enable
multiple exception state acceptance.
5.5.4
The RTE instruction is used to return from exception handling. When the RTE instruction is
executed, the SPC contents are restored to PC and the SSR contents to SR, and the CPU returns
from the exception handling routine by branching to the SPC address. If SPC and SSR were saved
to external memory, set the BL bit in SR to 1 before restoring the SPC and SSR contents and
issuing the RTE instruction.
5.6
The various exception handling operations are described here, covering exception sources,
transition addresses, and processor operation when a transition is made.
Rev.7.00 Oct. 10, 2008 Page 158 of 1074
REJ09B0366-0700
Exception Requests and BL Bit
Return from Exception Handling
Description of Exceptions
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