HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 582

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
Rev.7.00 Oct. 10, 2008 Page 496 of 1074
REJ09B0366-0700
CKIO
CS3
RD/WR
RAS
CASS
DQMn
D63−D0
BS
CKE
Notes: 1. The interval cycle number between the first and second REF commands is 4 + TRrw × m (m = 0 to 7)
Figure 13.46 Synchronous DRAM Auto-Refresh Timing with 64-Bit Bus Width
2. The interval cycle number between the second REF command and the ACTV command after the refresh
3. The next ACTV command is issued at TRr3 to TRr5 (including TRrw × m) + 3Trc × n (n = 0 to 7) + 1
CKIO cycles by the setting of the TRAS[2:0] bits.
operation is 4 + TRrw × m (m = 0 to 7) + 3Trc × n (n = 0 to 7) CKIO cycles by the setting of the TRAS[2:0]
bits and the TRC[2:0] bits.
CKIO cycles after second REF command in this refresh operation. This 1 CKIO cycle is included in the
setting of the TRAS[2:0] bits. Set MCR.TRAS[2:0], MCR.TRC[2:0], RTCOR and RTCSR.CKS[2:0] so as
to satisfy the specification of the synchronous DRAM.
TRr1
TRr2 TRr3 TRr4
(TRAS[2:0] = 001, TRC[2:0] = 001)
MCR.TRAS[2:0]
TRrw*
1
TRr1
TRr2 TRr3 TRr4 TRrw*
MCR.TRAS[2:0] and MCR.TRC[2:0]
2
TRr5
Trc*
2
Trc*
2
Trc*
2
*
3