HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 92

MPU 1.5/3.3V 0K I-TEMP PB-FREE 2

HD6417750RF200DV

Manufacturer Part Number
HD6417750RF200DV
Description
MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF200DV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.35 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750RF200DV
Manufacturer:
FREESCALE
Quantity:
450
Section 1 Overview
Item
Interrupt controller
(INTC)
User break
controller (UBC)
Bus state
controller (BSC)
Rev.7.00 Oct. 10, 2008 Page 6 of 1074
REJ09B0366-0700
Features
Five independent external interrupts: NMI, IRL3 to IRL0
15-level encoded external interrupts: IRL3 to IRL0
On-chip peripheral module interrupts: Priority level can be set for each
module
Supports debugging by means of user break interrupts
Two break channels
Address, data value, access type, and data size can all be set as break
conditions
Supports sequential break function
Supports external memory access
⎯ 64/32/16/8-bit external data bus
External memory space divided into seven areas, each of up to 64
Mbytes, with the following parameters settable for each area:
⎯ Bus size (8, 16, 32, or 64 bits)
⎯ Number of wait cycles (hardware wait function also supported)
⎯ Connection of DRAM, synchronous DRAM, and burst ROM possible
⎯ Supports fast page mode and DRAM EDO
⎯ Supports PCMCIA interface
⎯ Chip select signals (CS0 to CS6) output for relevant areas
DRAM/synchronous DRAM refresh functions
⎯ Programmable refresh interval
⎯ Supports CAS-before-RAS refresh mode and self-refresh mode
DRAM/synchronous DRAM burst access function
Big endian or little endian mode can be set
by setting space type

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