MC912DG128ACPV Freescale Semiconductor, MC912DG128ACPV Datasheet

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MC912DG128ACPV

Manufacturer Part Number
MC912DG128ACPV
Description
IC MCU 128K FLASH 8MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC912DG128ACPV

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Freescale Semiconductor, Inc.
MC68HC912DT128A
MC68HC912DG128A
MC68HC912DT128C
MC68HC912DG128C
MC68HC912DT128P
MC68HC912DG128P
Technical Data
M68HC12
Microcontrollers
MC912DT128A/D
Rev. 4, 10/2003
MOTOROLA.COM/SEMICONDUCTORS
For More Information On This Product,
Go to: www.freescale.com

MC912DG128ACPV Summary of contents

Page 1

... Freescale Semiconductor, Inc. M68HC12 Microcontrollers MOTOROLA.COM/SEMICONDUCTORS For More Information On This Product, Go to: www.freescale.com MC68HC912DT128A MC68HC912DG128A MC68HC912DT128C MC68HC912DG128C MC68HC912DT128P MC68HC912DG128P Technical Data MC912DT128A/D Rev. 4, 10/2003 ...

Page 2

... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...

Page 3

... Freescale Semiconductor, Inc. MC68HC912DT128A MC68HC912DG128A MC68HC912DT128C MC68HC912DG128C MC68HC912DT128P MC68HC912DG128P Technical Data Rev 4.0 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any ...

Page 4

... Freescale Semiconductor, Inc. Technical Data 4 For More Information On This Product, Go to: www.freescale.com MC68HC912DT128A — Rev 4.0 MOTOROLA ...

Page 5

... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Technical Data — List of Paragraphs . . . . . . . . . . . . . . . . 5 Technical Data — Table of Contents Technical Data — List of Figures . . . . . . . . . . . . . . . . . . 17 Technical Data — List of Tables . . . . . . . . . . . . . . . . . . . 21 Section 1. General Description . . . . . . . . . . . . . . . . . . . . 25 Section 2. Central Processing Unit . . . . . . . . . . . . . . . . . 35 Section 3. Pinout and Signal Descriptions . . . . . . . . . . . 41 Section 4. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Section 5 ...

Page 6

... Freescale Semiconductor, Inc. List of Paragraphs Section 17. Inter IC Bus . . . . . . . . . . . . . . . . . . . . . . . . . 301 Section 18. MSCAN Controller . . . . . . . . . . . . . . . . . . . . 325 Section 19. Analog-to-Digital Converter . . . . . . . . . . . . 367 Section 20. Development Support 395 Section 21. Electrical Specifications 421 Section 22. Appendix: Changes from MC68HC912DG128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 Section 23. Appendix: CGM Practical Aspects . . . . . . 447 Section 24. Appendix: Information on MC68HC912DT128A Mask Set Changes . . . . . . . . . . . . 457 Technical Data — ...

Page 7

... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A 1.1 1.2 1.3 1.4 1.5 1.6 1.7 2.1 2.2 2.3 2.4 2.5 2.6 MC68HC912DT128A — Rev 4.0 MOTOROLA For More Information On This Product, List of Paragraphs Table of Contents List of Figures List of Tables Section 1. General Description Contents ...

Page 8

... Freescale Semiconductor, Inc. Table of Contents 2.7 3.1 3.2 3.3 3.4 3.5 4.1 4.2 5.1 5.2 5.3 5.4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 Technical Data 8 For More Information On This Product, Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Section 3. Pinout and Signal Descriptions Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 MC68HC912DT128A Pin Assignments in 112-pin QFP Power Supply Pins ...

Page 9

... Freescale Semiconductor, Inc. 7.1 7.2 7.3 7.4 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 9.1 9.2 9.3 9.4 9.5 9.6 9.7 MC68HC912DT128A — Rev 4.0 MOTOROLA For More Information On This Product, Section 7. Bus Control and Input/Output Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Introduction ...

Page 10

... Freescale Semiconductor, Inc. Table of Contents 9.8 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 Register Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.1 11.2 11.3 11.4 12.1 12.2 12.3 12.4 12.5 12.6 Technical Data 10 For More Information On This Product, Programming EEDIVH and EEDIVL Registers 135 Section 10 ...

Page 11

... Freescale Semiconductor, Inc. 12.7 12.8 12.9 12.10 Real-Time Interrupt 186 12.11 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 12.12 Clock Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 13.1 13.2 13.3 13.4 13.5 14.1 14.2 14.3 14.4 15.1 15.2 15.3 15.4 15.5 MC68HC912DT128A — Rev 4.0 MOTOROLA For More Information On This Product, System Clock Frequency Formulae ...

Page 12

... Freescale Semiconductor, Inc. Table of Contents 16.1 16.2 16.3 16.4 16.5 16.6 17.1 17.2 17.3 17.4 17.5 17.6 17.7 18.1 18.2 18.3 18.4 18.5 18.6 18.7 18.8 18.9 18.10 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343 Technical Data 12 For More Information On This Product, Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Block diagram ...

Page 13

... Freescale Semiconductor, Inc. 18.11 Memory Map 345 18.12 Programmer’s Model of Message Storage . . . . . . . . . . . . . . .346 18.13 Programmer’s Model of Control Registers . . . . . . . . . . . . . . . 351 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 20.1 20.2 20.3 20.4 20.5 20.6 21.1 21.2 21.3 MC68HC912DT128A — Rev 4.0 ...

Page 14

... Freescale Semiconductor, Inc. Table of Contents Section 22. Appendix: Changes from MC68HC912DG128 22.1 22.2 23.1 23.2 23.3 23.4 24.1 24.2 24.3 24.4 24.5 24.6 24.7 24.8 24.9 24.10 Changes from Rev 2.0 to Rev 3 473 24.11 Changes from Rev 1.0 to Rev 2 475 Technical Data ...

Page 15

... Freescale Semiconductor, Inc. 24.12 Changes from first version (internal release, no MC68HC912DT128A — Rev 4.0 MOTOROLA For More Information On This Product, revision number) to Rev 1 .475 Table of Contents Go to: www.freescale.com Table of Contents Technical Data 15 ...

Page 16

... Freescale Semiconductor, Inc. Table of Contents Technical Data 16 For More Information On This Product, Table of Contents Go to: www.freescale.com MC68HC912DT128A — Rev 4.0 MOTOROLA ...

Page 17

... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Figure 1-1 1-2 2-1 3-1 3-2 3-3 3-4 3-5 6-1 6-2 11-1 STOP Key Wake-up Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12-1 Internal Clock Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12-2 PLL Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 12-3 Clock Loss during Normal Operation . . . . . . . . . . . . . . . . . . .164 12-4 No Clock at Power-On Reset ...

Page 18

... Freescale Semiconductor, Inc. List of Figures 15-3 8-Bit Pulse Accumulators Block Diagram . . . . . . . . . . . . . . . .245 15-4 16-Bit Pulse Accumulators Block Diagram . . . . . . . . . . . . . . .246 15-5 Block Diagram for Port7 with Output compare / Pulse 15-6 C3F-C0F Interrupt Flag Setting . . . . . . . . . . . . . . . . . . . . . . .247 16-1 Multiple Serial Interface Block Diagram . . . . . . . . . . . . . . . . .278 16-2 Serial Communications Interface Block Diagram ...

Page 19

... Freescale Semiconductor, Inc. 21-3 STOP Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .431 21-4 WAIT Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . . 432 21-5 Interrupt Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 21-6 Port Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .434 21-7 Port Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .434 21-8 Multiplexed Expansion Bus Timing Diagram . . . . . . . . . . . . . 436 21-9 SPI Timing Diagram ( 438 21-9 A) SPI Slave Timing (CPHA = 0) ...

Page 20

... Freescale Semiconductor, Inc. List of Figures Technical Data 20 For More Information On This Product, List of Figures Go to: www.freescale.com MC68HC912DT128A — Rev 4.0 MOTOROLA ...

Page 21

... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Table 1-1 1-2 2-1 2-2 3-1 3-2 3-3 3-4 4-1 5-1 6-1 6-2 6-3 6-4 6-5 6-6 7-1 9-1 9-2 9-3 9-4 10-1 Interrupt Vector Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10-2 Stacking Order on Entry to Interrupts . . . . . . . . . . . . . . . . . . . 147 12-1 Summary of STOP Mode Exit Conditions .174 12-2 Summary of Pseudo STOP Mode Exit Conditions ...

Page 22

... Freescale Semiconductor, Inc. List of Tables 14-1 Clock A and Clock B Prescaler 230 14-2 PWM Left-Aligned Boundary Conditions . . . . . . . . . . . . . . . . 240 14-3 PWM Center-Aligned Boundary Conditions . . . . . . . . . . . . . . 240 15-1 Compare Result Output Action . . . . . . . . . . . . . . . . . . . . . . . . 255 15-2 Edge Detector Circuit Configuration . . . . . . . . . . . . . . . . . . . .256 15-3 Prescaler Selection 258 16-1 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280 16-2 Loop Mode Functions ...

Page 23

... Freescale Semiconductor, Inc. 20-7 Breakpoint Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 20-8 Breakpoint Address Range Control . . . . . . . . . . . . . . . . . . . . 416 20-9 Breakpoint Read/Write Control . . . . . . . . . . . . . . . . . . . . . . . . 418 20-10 Tag Pin Function .420 21-1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422 21-2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 21-3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .424 21-4 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 21-5 ATD DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 425 21-6 Analog Converter Characteristics (Operating) ...

Page 24

... Freescale Semiconductor, Inc. List of Tables Technical Data 24 For More Information On This Product, List of Tables Go to: www.freescale.com MC68HC912DT128A — Rev 4.0 MOTOROLA ...

Page 25

... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A 1.1 Contents 1.2 1.3 1.4 1.5 1.6 1.7 1.2 Introduction The MC68HC912DT128A microcontroller unit (MCU 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (CPU12), 128K bytes of flash EEPROM, 8K bytes of RAM, 2K bytes of EEPROM, two asynchronous serial communications ...

Page 26

... Freescale Semiconductor, Inc. General Description 1.3 Devices Covered in this Document The MC68HC912DG128A device is similar to the MC68HC912DT128A, but it has only two MSCAN12 modules. The entire databook applies to both devices, except where differences are noted. The MC68HC912DT128C and MC68HC912DT128P are devices similar to the MC68HC912DT128A, but with different oscillator configurations. ...

Page 27

... Freescale Semiconductor, Inc. • • • • MC68HC912DT128A — Rev 4.0 MOTOROLA For More Information On This Product, Memory – 128K byte flash EEPROM, made of four 32K byte modules with 8K bytes protected BOOT section in each module – 2K byte EEPROM – 8K byte RAM with Vstby, made of two 4K byte modules. ...

Page 28

... Freescale Semiconductor, Inc. General Description • • • • • Technical Data 28 For More Information On This Product, 4 PWM channels with programmable period and duty cycle – 8-bit 4-channel or 16-bit 2-channel – Separate control for each pulse width and duty cycle – Center- or left-aligned outputs – ...

Page 29

... Freescale Semiconductor, Inc. • • MC68HC912DT128A — Rev 4.0 MOTOROLA For More Information On This Product, 112-Pin TQFP package – general-purpose I/O lines on the MC68HC912DT128A ( the MC68HC912DG128A), plus input-only lines – 5.0V operation at 8 MHz Development support – Single-wire background debug™ mode (BDM) – ...

Page 30

... Freescale Semiconductor, Inc. General Description 1.5 MC68HC912DT128A Block Diagram 128K byte flash EEPROM VSTBY 8K byte RAM 2K byte EEPROM CPU12 Single-wire background BKGD debug module Clock XFC PLL Generation VDDPLL module VSSPLL EXTAL XTAL RESET PE0 XIRQ PE1 IRQ PE2 R/W PE3 ...

Page 31

... Freescale Semiconductor, Inc. 1.6 MC68HC912DG128A Block Diagram 128K byte flash EEPROM VSTBY 8K byte RAM 2K byte EEPROM CPU12 Single-wire background BKGD debug module Clock XFC PLL Generation VDDPLL module VSSPLL EXTAL XTAL RESET PE0 XIRQ PE1 IRQ PE2 R/W PE3 LSTRB PE4 ...

Page 32

... M –40 to +85°C C –40 to +105°C V –40 to +125°C M –40 to +85°C C –40 to +105°C V –40 to +125°C M General Description Go to: www.freescale.com Order Number MC912DG128ACPV MC912DG128AVPV MC912DG128AMPV MC912DT128ACPV MC912DT128AVPV MC912DT128AMPV MC912DG128CCPV MC912DG128CVPV MC912DG128CMPV MC912DT128CCPV MC912DT128CVPV MC912DT128CMPV MC912DG128PCPV MC912DG128PVPV MC912DG128PMPV MC912DT128PCPV MC912DT128PVPV MC912DT128PMPV MC68HC912DT128A — ...

Page 33

... Freescale Semiconductor, Inc. Table 1-2. Development Tools Ordering Information Description Evaluation board kit Low voltage serial debug interface cable can be Serial Debug Interface Complete evaluation EVB, MCUez debug software, SDIL low voltage serial board kit Adapter MC68HC912DT128A — Rev 4.0 MOTOROLA ...

Page 34

... Freescale Semiconductor, Inc. General Description Technical Data 34 For More Information On This Product, General Description Go to: www.freescale.com MC68HC912DT128A — Rev 4.0 MOTOROLA ...

Page 35

... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A 2.1 Contents 2.2 2.3 2.4 2.5 2.6 2.7 2.2 Introduction The CPU12 is a high-speed, 16-bit processing unit. It has full 16-bit data paths and wider internal registers ( bits) for high-speed extended math instructions. The instruction set is a proper superset of the M68HC11instruction set ...

Page 36

... Freescale Semiconductor, Inc. Central Processing Unit 2.3 Programming Model CPU12 registers are an integral part of the CPU and are not addressed as if they were memory locations Accumulators A and B are general-purpose 8-bit accumulators used to hold operands and results of arithmetic calculations or data manipulations. Some instructions treat the combination of these two 8- bit accumulators as a 16-bit double accumulator (accumulator D) ...

Page 37

... Freescale Semiconductor, Inc. Stack pointer (SP) points to the last stack location used. The CPU12 supports an automatic program stack that is used to save system context during subroutine calls and interrupts, and can also be used for temporary storage of data. The stack pointer can also be used in all indexed addressing modes ...

Page 38

... Freescale Semiconductor, Inc. Central Processing Unit 2.5 Addressing Modes Addressing modes determine how the CPU accesses memory locations to be operated upon. The CPU12 includes all of the addressing modes of the M68HC11 CPU as well as several new forms of indexed addressing. Table 2-1. M68HC12 Addressing Mode Summary ...

Page 39

... Freescale Semiconductor, Inc. 2.6 Indexed Addressing Modes The CPU12 indexed modes reduce execution time and eliminate code size penalties for using the Y index register. CPU12 indexed addressing uses a postbyte plus zero, one, or two extension bytes after the instruction opcode. The postbyte and extensions do the following tasks: • ...

Page 40

... Freescale Semiconductor, Inc. Central Processing Unit 2.7 Opcodes and Operands The CPU12 uses 8-bit opcodes. Each opcode identifies a particular instruction and associated addressing mode to the CPU. Several opcodes are required to provide each instruction with a range of addressing capabilities. Only 256 opcodes would be available if the range of values were restricted to the number that can be represented by 8-bit binary numbers ...

Page 41

... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 3. Pinout and Signal Descriptions 3.1 Contents 3.2 3.3 3.4 3.5 3.2 MC68HC912DT128A Pin Assignments in 112-pin QFP The MC68HC912DT128A is available in a 112-pin thin quad flat pack (TQFP). Most pins perform two or more functions, as described in the ...

Page 42

... Freescale Semiconductor, Inc. Pinout and Signal Descriptions PW2/PP2 1 2 PW1/PP1 3 PW0/PP0 IOC0/PT0 4 5 IOC1/PT1 6 IOC2/PT2 IOC3/PT3 7 8 KWJ7/PJ7 9 KWJ6/PJ6 KWJ5/PJ5 10 11 KWJ4/PJ4 PK3 IOC4/PT4 15 16 IOC5/PT5 17 IOC6/PT6 IOC7/PT7 18 19 KWJ3/PJ3 20 KWJ2/PJ2 KWJ1/PJ1 21 22 KWJ0/PJ0 23 SMODN/TAGHI/BKGD ADDR0/DATA0/PB0 24 25 ADDR1/DATA1/PB1 26 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 27 28 ADDR4/DATA4/PB4 Note: TEST = This pin is used for factory test purposes ...

Page 43

... Freescale Semiconductor, Inc. 1 PW2/PP2 PW1/PP1 2 3 PW0/PP0 4 IOC0/PT0 IOC1/PT1 5 6 IOC2/PT2 7 IOC3/PT3 KWJ7/PJ7 8 9 KWJ6/PJ6 10 KWJ5/PJ5 KWJ4/PJ4 PK3 IOC4/PT4 IOC5/PT5 16 17 IOC6/PT6 18 IOC7/PT7 KWJ3/PJ3 19 20 KWJ2/PJ2 21 KWJ1/PJ1 KWJ0/PJ0 22 23 SMODN/TAGHI/BKGD 24 ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 25 26 ADDR2/DATA2/PB2 27 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4 28 Note: TEST = This pin is used for factory test purposes recommended that this pin is not connected in the application, but it may be bonded to 5 ...

Page 44

... Freescale Semiconductor, Inc. Pinout and Signal Descriptions 0. PIN 1 112 IDENT 1 VIEW 0.050 θ C1 VIEW AB Figure 3-3. 112-pin QFP Mechanical Dimensions (case no. 987) Technical Data 44 For More Information On This Product, 0. TIPS VIEW AB θ 2 0.10 T 112X SEATING PLANE θ ...

Page 45

... Freescale Semiconductor, Inc. 3.3 Power Supply Pins MC68HC912DT128A power and ground pins are described below and summarized in All power supply pins must be connected to appropriate supplies account must any pins be left floating. 3.3.1 Internal Power (V ) and Ground (V DD Power is supplied to the MCU through V ...

Page 46

... Freescale Semiconductor, Inc. Pinout and Signal Descriptions 3.3 DDPLL SSPLL Provides operating voltage and ground for the Phase-Locked Loop. This allows the supply voltage to the PLL to be bypassed independently. NOTE: The VSSPLL pin should always be grounded even if the PLL is not used. ...

Page 47

... Freescale Semiconductor, Inc. 3.3.7 V STBY Stand-by voltage supply to static RAM. Used to maintain the contents of RAM with minimal power when the rest of the chip is powered down. Table 3-1. MC68HC912DT128A Power and Ground Connection Summary Pin Number Mnemonic 112-pin QFP V 12 Internal power and ground. ...

Page 48

... Freescale Semiconductor, Inc. Pinout and Signal Descriptions NOTE: When selecting a crystal recommended to use one with the lowest possible frequency in order to minimise EMC emissions. 3.4.1.2 External Oscillator Connections XTAL is the crystal output. The XTAL pin must be left unterminated when an external CMOS compatible clock input is connected to the EXTAL pin ...

Page 49

... Freescale Semiconductor, Inc. output to indicate that an internal failure has been detected in either the clock monitor or COP watchdog circuit. The MCU goes into reset asynchronously and comes out of reset synchronously. This allows the part to reach a proper reset state even if the clocks have failed, while allowing synchronized operation when starting out of reset ...

Page 50

... Freescale Semiconductor, Inc. Pinout and Signal Descriptions vector ($FFFA:FFFB). If neither clock monitor fail nor COP timeout are pending, processing begins by fetching the normal reset vector ($FFFE:FFFF). 3.4.4 Maskable Interrupt Request (IRQ) The IRQ input provides a means of applying asynchronous interrupt requests to the MCU. Either falling edge-sensitive triggering or level- sensitive triggering is program selectable (INTCR register) ...

Page 51

... Freescale Semiconductor, Inc. 3.4.5 Nonmaskable Interrupt (XIRQ) The XIRQ input provides a means of requesting a nonmaskable interrupt after reset initialization. During reset, the X bit in the condition code register (CCR) is set and any interrupt is masked until MCU software enables it. Because the XIRQ input is level sensitive, it can be connected to a multiple-source wired-OR network ...

Page 52

... Freescale Semiconductor, Inc. Pinout and Signal Descriptions 3.4.8 External Address and Data Buses (ADDR[15:0] and DATA[15:0]) External bus pins share functions with general-purpose I/O ports A and B. In single-chip operating modes, the pins can be used for I/O; in expanded modes, the pins are used for the external buses. ...

Page 53

... Freescale Semiconductor, Inc. 3.4.11 Instruction Queue Tracking Signals (IPIPE1 and IPIPE0) IPIPE1 (PE6) and IPIPE0 (PE5) signals are used to track the state of the internal instruction queue. Data movement and execution state information is time-multiplexed on the two signals. Refer to Support. 3.4.12 Data Bus Enable (DBE) The DBE pin (PE7 active low signal that will be asserted low during E-clock high time ...

Page 54

... Freescale Semiconductor, Inc. Pinout and Signal Descriptions 3.4.15 Clock generation module test (CGMTST) The CGMTST pin (PE6) is the output of the clocks tested when CGMTE bit is set in PEAR register. The PIPOE bit must be cleared for the clocks to be tested. 3.4.16 TEST This pin is used for factory test purposes recommended that this pin is not connected in the application, but it may be bonded to 5 ...

Page 55

... Freescale Semiconductor, Inc. Table 3-2. MC68HC912DT128A Signal Description Summary Pin Shared Number Pin Name port 112-pin Maskable interrupt request input provides a means of applying asynchronous IRQ PE1 55 Provides a means of requesting asynchronous nonmaskable interrupt requests XIRQ PE0 56 During reset, this pin determines special or normal operating mode. After reset, ...

Page 56

... Freescale Semiconductor, Inc. Pinout and Signal Descriptions Table 3-2. MC68HC912DT128A Signal Description Summary Pin Shared Number Pin Name port 112-pin SDA PIB6 99 I 8–11, Key wake-up and general purpose I/O; can cause an interrupt when an input KWJ[7:0] PJ[7:0] 19–22 32–35, Key wake-up and general purpose I/O; can cause an interrupt when an input ...

Page 57

... Freescale Semiconductor, Inc. Setting the RDPA bit in register RDRIV causes all port A outputs to have reduced drive level. RDRIV can be written once after reset. RDRIV is not in the address map in peripheral mode. Refer to Input/Output. 3.5.2 Port B Port B pins are used for address and data in expanded modes. When this port is not used for external access such as in single-chip mode, these pins can be used as general purpose I/O ...

Page 58

... Freescale Semiconductor, Inc. Pinout and Signal Descriptions general-purpose I/O. PEAR settings override DDRE settings. Because PE[1:0] are input-only pins, only DDRE[7:2] have effect. Setting a bit in the DDRE register makes the corresponding bit in port E an output; clearing a bit in the DDRE register makes the corresponding bit in port E an input ...

Page 59

... Freescale Semiconductor, Inc. Setting the RDPH bit in register RDRIV causes all port H outputs to have reduced drive level. RDRIV can be written once after reset. RDRIV is not in the address map in peripheral mode. Refer to Input/Output. 3.5.5 Port J Port J pins are used for key wake-ups that can be used with the pins configured as inputs or outputs ...

Page 60

... Freescale Semiconductor, Inc. Pinout and Signal Descriptions for general purpose I/O. Port K bit 3 is used as a general purpose I/O pin only. The port data register is not in the address map during expanded and peripheral mode operation with EMK set. When the map, port K can be read or written at anytime ...

Page 61

... Freescale Semiconductor, Inc. 3.5.9 Port CAN0 The MSCAN0 uses two external pins, one input (RxCAN0) and one output (TxCAN0). The TxCAN0 output pin represents the logic level on the CAN: ‘0’ is for a dominant state, and ‘1’ is for a recessive state. RxCAN0 is on bit 0 of Port CAN0, TxCAN0 is on bit 1. If the MSCAN0 is not used, TxCAN0 should be left unconnected and, due to an internal pull-up, the RxCAN0 pin should not be tied to VSS ...

Page 62

... Freescale Semiconductor, Inc. Pinout and Signal Descriptions 3.5.11 Port AD1 This port is an analog input interface to the analog-to-digital subsystem and used for general-purpose input. When analog-to-digital functions are not enabled, the port has eight general-purpose input pins, PAD1[7:0]. The ADPU bit in the ATD1CTL2 register enables the A/D function. Port AD1 pins are inputs ...

Page 63

... Freescale Semiconductor, Inc. Setting the RDPP bit in the PWCTL register configures all port P outputs to have reduced drive levels. Levels are at normal drive capability after reset. The PWCTL register can be read or written anytime after reset. Refer to 3.5.14 Port S Port S is the 8-bit interface to the standard serial interface consisting of the two serial communications interfaces (SCI1 and SCI0) and the serial peripheral interface (SPI) subsystems ...

Page 64

... Freescale Semiconductor, Inc. Pinout and Signal Descriptions When the PUPT bit in the TMSK2 register is set, all input pins are pulled up internally by an active pull-up device. Pullups are disabled after reset. Setting the RDPT bit in the TMSK2 register configures all port T outputs to have reduced drive levels ...

Page 65

... Freescale Semiconductor, Inc. Pinout and Signal Descriptions Table 3-3. MC68HC912DT128A Port Description Summary Pin Data Direction Numbers Port Name Register (Address) 112-pin Port S In/Out 96–89 PS[7:0] DDRS ($00D7) Port T 18–15, In/Out PT[7:0] 7–4 DDRT ($00AF) only 1. MC68HC912DT128A only 2. MC68HC912DG128A 3.5.16 Port Pull-Up Pull-Down and Reduced Drive MCU ports can be configured for internal pull-up ...

Page 66

... Freescale Semiconductor, Inc. Pinout and Signal Descriptions Table 3-4. Port Pull-Up, Pull-Down and Reduced Drive Summary Port Resistive Register Name Input Loads (Address) (1) Pull-up IBPURD ($00E5) Port IB[5:4] Port AD0 None Port AD1 None Port None (2) CAN2[1] Port Pull-up (2) CAN2[0] Port CAN1[1] ...

Page 67

... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A 4.1 Contents 4.2 4.2 Register Block The register block can be mapped to any 2K byte boundary within the standard 64K byte address space by manipulating bits REG[15:11] in the INITRG register. INITRG establishes the upper five bits of the register block’ ...

Page 68

... Freescale Semiconductor, Inc. Registers Address Bit 7 6 $0000 PA7 PA6 $0001 PB7 PB6 $0002 DDA7 DDA6 $0003 DDB7 DDB6 $0004 $0007 $0008 PE7 PE6 $0009 DDE7 DDE6 $000A NDBE CGMTE PIPOE $000B SMODN MODB MODA $000C PUPK PUPJ $000D RDPK RDPJ ...

Page 69

... Freescale Semiconductor, Inc. Address Bit 7 6 $0024 Bit 15 14 $0025 Bit 7 6 $0026 0 0 $0027 0 0 $0028 PJ7 PJ6 $0029 PH7 PH6 $002A DDJ7 DDJ6 $002B DDH7 DDH6 $002C KWIEJ7 KWIEJ6 KWIEJ5 $002D KWIEH7 KWIEH6 KWIEH5 $002E KWIFJ7 KWIFJ6 KWIFJ5 $002F ...

Page 70

... Freescale Semiconductor, Inc. Registers Address Bit 7 6 $004C Bit 7 6 $004D Bit 7 6 $004E Bit 7 6 $004F Bit 7 6 $0050 Bit 7 6 $0051 Bit 7 6 $0052 Bit 7 6 $0053 Bit 7 6 $0054 0 0 $0055 DISCR DISCP DISCAL $0056 PP7 PP6 $0057 ...

Page 71

... Freescale Semiconductor, Inc. Address Bit 7 6 $007C Bit 15 14 $007D Bit 7 Bit 6 $007E Bit 15 14 $007F Bit 7 Bit 6 $0080 IOS7 IOS6 $0081 FOC7 FOC6 FOC5 $0082 OC7M7 OC7M6 OC7M5 $0083 OC7D7 OC7D6 OC7D5 $0084 Bit 15 14 $0085 Bit 7 6 $0086 TEN ...

Page 72

... Freescale Semiconductor, Inc. Registers Address Bit 7 6 $00A2 Bit 7 6 $00A3 Bit 7 6 $00A4 Bit 7 6 $00A5 Bit 7 6 $00A6 MCZI MODMC RDMCL $00A7 MCZF 0 $00A8 0 0 $00A9 0 0 $00AA NOVW7 NOVW6 NOVW5 $00AB SH37 SH26 $00AC 0 0 $00AD 0 0 $00AE ...

Page 73

... Freescale Semiconductor, Inc. Address Bit 7 6 $00C8 BTST BSPL $00C9 SBR7 SBR6 $00CA LOOPS WOMS $00CB TIE TCIE $00CC TDRE TC $00CD 0 0 $00CE R8 T8 $00CF R7/T7 R6/T6 $00D0 SPIE SPE SWOM $00D1 0 0 $00D2 0 0 $00D3 SPIF WCOL $00D4 0 0 $00D5 ...

Page 74

... Freescale Semiconductor, Inc. Registers Address Bit 7 6 $00F7 0 0 $00F8 MT07 MT06 $00F9 MT0F MT0E $00FA MT17 MT16 $00FB MT1F MT1E $00FC PK7 0 $00FD DDK7 0 $00FE 0 0 $00FF 0 0 $0100 0 0 CSWAI $0101 0 0 $0102 SJW1 SJW0 $0103 SAMP TSEG22 TSEG21 ...

Page 75

... Freescale Semiconductor, Inc. Address Bit 7 6 $0120– $013C $013D 0 0 $013E PCAN7 PCAN6 PCAN5 $013F DDCAN7 DDCAN6 DDCAN5 DDCAN4 DDCAN3 DDCAN2 $0140– $014F $0150– $015F $0160– $016F $0170– $017F $0180– $01DF $01E0 $01E1 $01E2 ADPU ...

Page 76

... Freescale Semiconductor, Inc. Registers Address Bit 7 6 $01FC Bit 15 14 $01FD Bit 7 Bit 6 $01FE Bit 15 14 $01FF Bit 7 Bit 6 ( CSWAI $0200 ( $0201 (7) SJW1 SJW0 $0202 (7) SAMP TSEG22 TSEG21 $0203 (7) WUPIF RWRNIF TWRNIF $0204 (7) WUPIE RWRNIE TWRNIE $0205 (7) 0 ABTAK2 ABTAK1 $0206 ...

Page 77

... Freescale Semiconductor, Inc. Address Bit 7 6 $0220– $023C ( $023D (7) PCAN7 PCAN6 PCAN5 $023E (7) $023F DDCAN7 DDCAN6 DDCAN5 DDCAN4 DDCAN3 DDCAN2 (7) $0240 – $024F (7) $0250 – $025F (7) $0260 – $026F (7) $0270 – $027F $0280- $02FF $0300 0 0 CSWAI $0301 0 0 $0302 ...

Page 78

... Freescale Semiconductor, Inc. Registers Address Bit 7 6 $031A AC7 AC6 $031B AC7 AC6 $031C AM7 AM6 $031D AM7 AM6 $031E AM7 AM6 $031F AM7 AM6 $0320– $033C $033D 0 0 $033E PCAN7 PCAN6 PCAN5 $033F DDCAN7 DDCAN6 DDCAN5 DDCAN4 DDCAN3 DDCAN2 $0340– ...

Page 79

... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A 5.1 Contents 5.2 5.3 5.4 5.2 Introduction Eight possible operating modes determine the operating configuration of the MC68HC912DT128A. Each mode has an associated default memory map and external bus configuration. 5.3 Operating Modes The operating mode out of reset is determined by the states of the BKGD, MODB, and MODA pins during reset ...

Page 80

... Freescale Semiconductor, Inc. Operating Modes BKGD MODB MODA There are two basic types of operating modes: A system development and debug feature, background debug mode (BDM), is available in all modes. In special single-chip mode, BDM is active immediately after reset. 5.3.1 Normal Operating Modes These modes provide three operating configurations. Background debug is available in all three modes, but must first be enabled for some operations by means of a BDM background command, then activated ...

Page 81

... Freescale Semiconductor, Inc. 5.3.2 Special Operating Modes There are three special operating modes that correspond to normal operating modes. These operating modes are commonly used in factory testing and system development. In addition, there is a special peripheral mode, in which an external master, such as an I.C. tester, can control the on-chip peripherals. MC68HC912DT128A — ...

Page 82

... Freescale Semiconductor, Inc. Operating Modes Bit 7 6 SMODN MODB MODA RESET RESET RESET RESET RESET RESET RESET MODE — Mode Register The MODE register controls the MCU operating mode and various configuration options. This register is not in the map in peripheral mode SMODN, MODB, MODA — Mode Select Special, B and A These bits show the current operating mode and reflect the status of the BKGD, MODB and MODA input pins at the rising edge of reset ...

Page 83

... Freescale Semiconductor, Inc. ESTR — E Clock Stretch Enable Determines if the E Clock behaves as a simple free-running clock bus control signal that is active only for external bus cycles. ESTR is always one in expanded modes since it is required for address and data de-multiplexing and must follow stretched cycles. ...

Page 84

... Freescale Semiconductor, Inc. Operating Modes EMK — Emulate Port K In single-chip mode PORTK and DDRK are always in the map regardless of the state of this bit Port K and DDRK registers are in the memory map. Memory expanded or peripheral mode, PORTK and DDRK are Normal modes: write once; special modes: write anytime EXCEPT the first time. Read anytime. EME — ...

Page 85

... Freescale Semiconductor, Inc. Once enabled, background mode can be made active by a serial command sent via the BKGD pin or execution of a CPU12 BGND instruction. While background mode is active, the CPU can interpret special debugging commands, and read and write CPU registers, peripheral registers, and locations in memory. ...

Page 86

... Freescale Semiconductor, Inc. Operating Modes Technical Data 86 For More Information On This Product, Operating Modes Go to: www.freescale.com MC68HC912DT128A — Rev 4.0 MOTOROLA ...

Page 87

... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A 6.1 Contents 6.2 6.3 6.4 6.5 6.6 6.7 6.2 Introduction After reset, most system resources can be mapped to other addresses by writing to the appropriate control registers. 6.3 Internal Resource Mapping The internal register block, RAM, and EEPROM have default locations ...

Page 88

... Freescale Semiconductor, Inc. Resource Mapping unintended operations, a write to one of these registers should be followed with a NOP instruction. If conflicts occur when mapping resources, the register block will take precedence over the other resources; RAM or EEPROM addresses occupied by the register block will not be available for storage. When active, BDM ROM takes precedence over other resources, although a conflict between BDM ROM and register space is not possible ...

Page 89

... Freescale Semiconductor, Inc. 6.3.1 Register Block Mapping After reset the 1K byte register block resides at location $0000 but can be reassigned to any 2K byte boundary within the standard 64K byte address space. Mapping of internal registers is controlled by five bits in the INITRG register. The register block occupies the first 1K byte of the 2K byte block. INITRG — ...

Page 90

... Freescale Semiconductor, Inc. Resource Mapping 6.3.2 RAM Mapping The MC68HC912DT128A has 8K bytes of fully static RAM that is used for storing instructions, variables, and temporary data during program execution. Since the RAM is actually implemented with two 4K RAM arrays, any misaligned word access between last address of first 4K RAM and first address of second 4K RAM will take two cycles instead of one ...

Page 91

... Freescale Semiconductor, Inc. 6.3.3 EEPROM Mapping The MC68HC912DT128A has 2K bytes of EEPROM which is activated by the EEON bit in the INITEE register. Mapping of internal EEPROM is controlled by four bits in the INITEE register. After reset EEPROM address space begins at location $0800 but can be mapped to any 4K byte boundary within the standard 64K byte address space. The EEPROM block occupies the last 2K bytes of the 4K byte block. INITEE— ...

Page 92

... Freescale Semiconductor, Inc. Resource Mapping 6.4 Flash EEPROM mapping through internal Memory Expansion The Page Index register or PPAGE provides memory management for the MC68HC912DT128A. PPAGE consists of three bits to indicate which physical location is active within the windows of the MC68HC912DT128A. The MC68HC912DT128A has a user’s program space window, a register space window for Flash module registers, and a test program space window ...

Page 93

... Freescale Semiconductor, Inc. Table 6-2. Program space Page Index Page Index 2 Page Index 1 Page Index 0 (PPAGE bit 2) (PPAGE bit 1) (PPAGE bit The 16K byte flash in program space page 6 can also be accessed at a fixed location from $4000 to $7FFF. The 16K byte flash in program space page 7 can also be accessed at a fixed location from $C000 to $FFFF ...

Page 94

... Freescale Semiconductor, Inc. Resource Mapping 6.4.3 Test mode Program space expansion In special mode and for test purposes only, the 128K bytes of Flash EEPROM for MC68HC912DT128A can be accessed through a test program space window of 32K bytes. This window replaces the user’s program space window to be able to access an entire array. In special mode and with ROMTST bit set in MISC register, a program space is located from $8000 to $FFFF ...

Page 95

... Freescale Semiconductor, Inc. When inputs, these pins can be selected to be high impedance or pulled up. ECS — Emulation Chip Select of selected program space When this signal is active low it indicates that the program space is accessed. This also applies to test mode program space. An access is made if address is at the program space window and either the Flash or external memory is accessed ...

Page 96

... Freescale Semiconductor, Inc. Resource Mapping PPAGE — (Program) Page Index Register Bit RESET Read and write: anytime. This register determines the active page viewed through MC68HC912DT128A windows. CALL and RTC instructions have a special single wire mechanism to read and write this register without using an address bus. ...

Page 97

... Freescale Semiconductor, Inc. NDRF — Narrow Data Bus for Register-Following Map Space This bit enables a narrow bus feature for the 1K byte Register- Following Map. This is useful for accessing 8-bit peripherals and allows 8-bit and 16-bit external memory devices to be mixed in a system. In Expanded Narrow (eight bit) modes, Single Chip Modes, and Peripheral mode, this bit has no effect ...

Page 98

... Freescale Semiconductor, Inc. Resource Mapping ROMHM — Flash EEPROM only in second Half of Map This bit has no meaning if ROMON bit is clear The 16K byte of fixed Flash EEPROM in location $4000-$7FFF 1 = Disables direct access to 16K byte Flash EEPROM from In special mode and with ROMTST bit set, this bit will allow overlap of ...

Page 99

... Freescale Semiconductor, Inc. 6.6 Mapping test registers These registers are used in for testing the mapping logic. They can only be read and after each read they get cleared. A write to each register will have no effect. MTST0 — Mapping Test Register 0 Bit 7 6 MT07 ...

Page 100

... Freescale Semiconductor, Inc. Resource Mapping 6.7 Memory Maps The following diagrams illustrate the memory map for each mode of operation immediately after reset. $0000 $0400 $0800 $1000 $2000 $4000 $8000 EXT $C000 $FF00 VECTORS VECTORS $FFFF NORMAL EXPANDED SINGLE CHIP . Figure 6-1 The following diagram illustrates the memory paging scheme ...

Page 101

... Freescale Semiconductor, Inc. $0000 $0400 $0800 $1000 $2000 $4000 6 16K Flash (Unpaged) 00 Flash 32K $8000 0 16K Flash (Paged) $C000 7 16K Flash $E000 (Unpaged) (8K Boot) $FF00 VECTORS $FFFF NORMAL SINGLE CHIP Figure 6-2 MC68HC912DT128A — Rev 4.0 MOTOROLA For More Information On This Product, ...

Page 102

... Freescale Semiconductor, Inc. Resource Mapping Technical Data 102 For More Information On This Product, Resource Mapping Go to: www.freescale.com MC68HC912DT128A — Rev 4.0 MOTOROLA ...

Page 103

... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A 7.1 Contents 7.2 7.3 7.4 7.2 Introduction Internally the MC68HC912DT128A has full 16-bit data paths, but depending upon the operating mode and control registers, the external multiplexed bus may bits. There are cases where 8-bit and 16-bit accesses can appear on adjacent cycles using the LSTRB signal to indicate 8- or 16-bit data ...

Page 104

... Freescale Semiconductor, Inc. Bus Control and Input/Output 7.4 Registers Not all registers are visible in the MC68HC912DT128A memory map under certain conditions. In special peripheral mode the first 16 registers associated with bus expansion are removed from the memory map. In expanded modes, some or all of port A, port B, and port E are used for expansion buses and control signals ...

Page 105

... Freescale Semiconductor, Inc. PORTA — Port A Register Bit 7 6 Single Chip PA7 PA6 RESET: — — Expanded ADDR15/ ADDR14/ & Periph: DATA15 DATA14 Expanded ADDR15/ ADDR14/ narrow DATA15/ DATA14/ DATA7 DATA6 Bits PA[7:0] are associated respectively with addresses ADDR[15:8], DATA[15:8] and DATA[7:0], in narrow mode. When this port is not used for external addresses such as in single-chip mode, these pins can be used as general-purpose I/O ...

Page 106

... Freescale Semiconductor, Inc. Bus Control and Input/Output PORTB — Port B Register Bit 7 6 Single Chip PB7 PB6 RESET: — — Expanded ADDR7/ ADDR6/ & Periph: DATA7 DATA6 Expanded ADDR7 ADDR6 narrow Bits PB[7:0] are associated with addresses ADDR[7:0] and DATA[7:0] (except in narrow mode) respectively. When this port is not used for external addresses such as in single-chip mode, these pins can be used as general-purpose I/O ...

Page 107

... Freescale Semiconductor, Inc. (R/W), IRQ, and XIRQ. When the associated pin is not used for one of these specific functions, the pin can be used as general-purpose I/O. The port E assignment register (PEAR) selects the function of each pin. DDRE determines the primary direction of each port E pin when configured to be general-purpose I/O ...

Page 108

... Freescale Semiconductor, Inc. Bus Control and Input/Output PEAR — Port E Assignment Register BIT 7 6 NDBE CGMTE RESET RESET RESET RESET RESET Port E serves as general purpose I/O lines or as system and bus control signals. The PEAR register is used to choose between the general-purpose I/O functions and the alternate bus control functions. ...

Page 109

... Freescale Semiconductor, Inc. In peripheral mode, the PEAR register is not accessible for reads or writes. However, the CGMTE control bit is reset to one to configure PE6 as a test output for the CGM module. NDBE — No Data Bus Enable Normal: write once; Special: write anytime EXCEPT the first. Read anytime ...

Page 110

... Freescale Semiconductor, Inc. Bus Control and Input/Output 0 = PE4 is the external E-clock pin subject to the following 1 = PE4 is a general-purpose I/O pin. LSTRE — Low Strobe (LSTRB) Enable Normal: write once; Special: write anytime EXCEPT the first time. Read anytime. This bit has no effect in single-chip modes or normal expanded narrow mode ...

Page 111

... Freescale Semiconductor, Inc. CALE — Calibration Reference Enable Read and write anytime. DBENE — DBE or Inverted E Clock on PE7 Normal modes: write once. Special modes: write anytime EXCEPT the first time. Read anytime. DBENE controls which signal is output on PE7 when NDBE control bit is cleared ...

Page 112

... Freescale Semiconductor, Inc. Bus Control and Input/Output PUPJ — Pull-Up or Pull-Down Port J Enable 0 = Port J resistive loads (pull-ups or pull-downs) are disabled Enable resistive load devices (pull-ups or pull-downs) for all PUPH — Pull-Up or Pull-Down Port H Enable 0 = Port H resistive loads (pull-ups or pull-downs) are disabled. ...

Page 113

... Freescale Semiconductor, Inc. RDRIV — Reduced Drive of I/O Lines Bit 7 6 RDPK RDPJ RESET These bits select reduced drive for the associated port pins. This gives reduced power consumption and reduced RFI with a slight increase in transition time (depending on loading). The reduced drive function is independent of which function is being used on a particular port ...

Page 114

... Freescale Semiconductor, Inc. Bus Control and Input/Output Technical Data 114 For More Information On This Product, Bus Control and Input/Output Go to: www.freescale.com MC68HC912DT128A — Rev 4.0 MOTOROLA ...

Page 115

... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A 8.1 Contents 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.2 Introduction The four Flash EEPROM array modules 00FEE32K, 01FEE32K, 10FEE32K and 11FEE32K for the MC68HC912DT128A serve as electrically erasable and programmable, non-volatile ROM emulation memory ...

Page 116

... Freescale Semiconductor, Inc. Flash Memory 8.3 Overview Each 32K Flash EEPROM array is arranged in a 16-bit configuration and may be read as either bytes, aligned words or misaligned words. Access time is one bus cycle for byte and aligned word access and two bus cycles for misaligned word operations. ...

Page 117

... Freescale Semiconductor, Inc. fixed 32K Flash EEPROM array 11FEE32K. In expanded modes, the Flash EEPROM arrays are turned off. See 8.6 Flash EEPROM Registers Each 32K byte Flash EEPROM module has a set of registers. The register space $00F4-$00F7 register space window of four pages. ...

Page 118

... Freescale Semiconductor, Inc. Flash Memory BOOTP — Boot Protect The boot blocks are located at $E000–$FFFF and $A000–$BFFF for odd program pages for each Flash EEPROM module. Since boot programs must be available at all times, the only useful boot block is at $E000– ...

Page 119

... Freescale Semiconductor, Inc. PGM — Program Control This bit configures the memory for program operation. PGM is interlocked with the ERAS bit such that both bits cannot be equal set to1 at the same time Program operation is not selected Program operation selected. 8.7 Operation The Flash EEPROM can contain program and data ...

Page 120

... Freescale Semiconductor, Inc. Flash Memory Programming and erasing of Flash locations cannot be performed by code being executed from the Flash memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Do not exceed t 8.8 Programming the Flash EEPROM Programming the Flash EEPROM is done on a row basis ...

Page 121

... Freescale Semiconductor, Inc. 12. After time, t This program sequence is repeated throughout the memory until all data is programmed. For minimum overall programming time and least program disturb effect, the sequence should be part of an intelligent operation which iterates per row. 8.9 Erasing the Flash EEPROM The following sequence demonstrates the recommended procedure for erasing any of the Flash EEPROM array ...

Page 122

... Freescale Semiconductor, Inc. Flash Memory 8.11 Flash protection bit FPOPEN The FPOPEN bit is located in EEMCR – EEPROM Module Configuration Register, bit 4. FPOPEN – Opens the Flash array for program or erase 0 = The whole Flash array is protected The whole Flash array is enabled for program or erase FPOPEN can be read at anytime. FPOPEN can be written only to ’ ...

Page 123

... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A 9.1 Contents 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.2 Introduction The MC68HC912DT128A EEPROM nonvolatile memory is arranged in a 16-bit configuration. The EEPROM array may be read as either bytes, aligned words or misaligned words. Access times are one bus cycle for byte and aligned word access and two bus cycles for misaligned word operations ...

Page 124

... Freescale Semiconductor, Inc. EEPROM Memory 9.3 EEPROM Selective Write More Zeros The EEPROM can be programmed such that one or multiple bits are programmed (written to a logic “0” time. However, the user should never program any bit more than once before erasing the entire byte. In other words, the user is not allowed to over write a logic “ ...

Page 125

... Freescale Semiconductor, Inc. 9.4 EEPROM Programmer’s Model The EEPROM module consists of two separately addressable sections. The first is an eight-byte memory mapped control register block used for control, testing and configuration of the EEPROM array. The second section is the EEPROM array itself. ...

Page 126

... Freescale Semiconductor, Inc. EEPROM Memory A steady internal self-time clock is required to provide accurate counts to meet EEPROM program/erase requirements. This clock is generated via by a programmable 10-bit prescaler register. Automatic program/erase termination is also provided. In ordinary situations, with crystal operating properly, the steady internal self-time clock is derived from the input clock source (EXTALi). The divider value EEDIVH:EEDIVL ...

Page 127

... Freescale Semiconductor, Inc. EEDIV[9:0] — Prescaler divider Loaded from SHADOW word at reset. Read anytime. Write once in normal modes (SMODN =1) if EELAT = 0 and anytime in special modes (SMODN =0) if EELAT = 0. The prescaler divider is required to produce a self-time clock with a fixed frequency around 28.6 Khz for the range of oscillator frequencies. The divider is set so that the oscillator frequency can be divided by a divide factor that can produce a 35 µ ...

Page 128

... Freescale Semiconductor, Inc. EEPROM Memory EEMCR — EEPROM Module Configuration Bit 7 6 NOBDML NOSHW Reserved (3) (3) RESET: — — 1. Bit 5 has a test function and should not be programmed. 2. The FPOPEN bit is available only on the 0L05H and later mask sets. For previous masks, this bit is reserved. ...

Page 129

... Freescale Semiconductor, Inc. FPOPEN — Opens the Flash Block for Program or Erase 0 = The whole Flash array is protected The whole Flash array is enable for program or erase. Loaded from SHADOW word at reset. Read anytime. Write anytime in special modes (SMODN=0). Write once ’0’ is allowed in normal mode. EESWAI — ...

Page 130

... Freescale Semiconductor, Inc. EEPROM Memory EEPROT — EEPROM Block Protect Bit 7 6 SHPROT 1 RESET Prevents accidental writes to EEPROM. Read anytime. Write anytime if EEPGM = 0 and PROTLCK = 0. SHPROT — SHADOW Word Protection BPROT[5:0] — EEPROM Block Protection EETST — EEPROM Test Bit EREVTN ...

Page 131

... Freescale Semiconductor, Inc. . EEPROG — EEPROM Control Bit 7 6 BULKP 0 RESET BULKP — Bulk Erase Protection 0 = EEPROM can be bulk erased EEPROM is protected from being bulk or row erased. Read anytime. Write anytime if EEPGM = 0 and PROTLCK = 0. AUTO — Automatic shutdown of program/erase operation. EEPGM is cleared automatically after the program/erase cycles are finished when AUTO is set ...

Page 132

... Freescale Semiconductor, Inc. EEPROM Memory ERASE — Erase Control 0 = EEPROM configuration for programming EEPROM configuration for erasure. Read anytime. Write anytime if EEPGM = 0. Configures the EEPROM for erasure or programming. Unless BULKP is set, erasure is by byte, aligned word, row or bulk. EELAT — EEPROM Latch Control 0 = EEPROM set up for normal reads ...

Page 133

... Freescale Semiconductor, Inc. 9.6 Program/Erase Operation A program or erase operation should follow the sequence below if AUTO bit is clear: 1. Write BYTE, ROW and ERASE to desired value, write EELAT = 1 2. Write a byte or an aligned word to an EEPROM address 3. Write EEPGM = 1 4. Wait for programming, 5 ...

Page 134

... Freescale Semiconductor, Inc. EEPROM Memory 9.7 Shadow Word Mapping The shadow word is mapped to location $_FC0 and $_FC1 when the NOSHW bit in EEMCR register is zero. The value in the shadow word is loaded to the EEMCR, EEDIVH and EEDIVL after reset. shows the mapping of each bit from shadow word to the registers. ...

Page 135

... Freescale Semiconductor, Inc. 9.8 Programming EEDIVH and EEDIVL Registers The EEDIVH and EEDIVL registers must be correctly set according to the oscillator frequency before any EEPROM location can be programmed or erased. 9.8.1 Normal mode The EEDIVH and EEDIVL registers are write once in normal mode. ...

Page 136

... Freescale Semiconductor, Inc. EEPROM Memory 5. Program bits 1 and 0 of the high byte of the SHADOW word and 6. Protect the SHADOW word by setting SHPROT bit in EEPROT Technical Data 136 For More Information On This Product, bits the low byte of the SHADOW word like a regular EEPROM location at address $0FC0 and $0FC1. Do not program other bits of the high byte of the SHADOW word (location $0FC0) ...

Page 137

... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A 10.1 Contents 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 Register Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 10.2 Introduction CPU12 exceptions include resets and interrupts. Each exception has an associated 16-bit vector, which points to the memory location where the routine that handles the exception is located ...

Page 138

... Freescale Semiconductor, Inc. Resets and Interrupts 10.3 Exception Priority A hardware priority hierarchy determines which reset or interrupt is serviced first when simultaneous requests are made. Six sources are not maskable. The remaining sources are maskable, and any one of them can be given priority over other maskable interrupts. ...

Page 139

... Freescale Semiconductor, Inc. 10.5 Latching of Interrupts XIRQ is always level triggered and IRQ can be selected as a level triggered interrupt. These level triggered interrupt pins should only be released during the appropriate interrupt service routine. Generally the interrupt service routine will handshake with the interrupting logic to release the pin ...

Page 140

... Freescale Semiconductor, Inc. Resets and Interrupts Vector Address Interrupt Source $FFFE, $FFFF Reset $FFFC, $FFFD Clock monitor fail reset $FFFA, $FFFB COP failure reset $FFF8, $FFF9 Unimplemented instruction trap $FFF6, $FFF7 SWI $FFF4, $FFF5 XIRQ $FFF2, $FFF3 IRQ $FFF0, $FFF1 Real time interrupt ...

Page 141

... Freescale Semiconductor, Inc. Vector Address Interrupt Source $FFBC, $FFBD MSCAN 1 errors $FFBA, $FFBB MSCAN 1 receive $FFB8, $FFB9 MSCAN 1 transmit (1) MSCAN 2 wake-up $FFB6, $FFB7 (1) MSCAN 2 errors $FFB4, $FFB5 (1) MSCAN 2 receive $FFB2, $FFB3 (1) MSCAN 2 transmit $FFB0, $FFB1 $FF80–$FFAF Reserved 1. MC68HC912DT128A only 10.6 Interrupt Control and Priority Registers INTCR — ...

Page 142

... Freescale Semiconductor, Inc. Resets and Interrupts IRQEN can be read and written anytime in all modes. DLY — Enable Oscillator Start-up Delay on Exit from STOP The delay time of about 4096 cycles is based on the XCLK rate chosen stabilization delay imposed on exit from STOP mode Stabilization delay is imposed before processing resumes after DLY can be read anytime and written once in normal modes ...

Page 143

... Freescale Semiconductor, Inc. These registers can only be read in special modes (read in normal mode will return $00). Reading these registers at the same time as the interrupt is changing will cause an indeterminate value to be read. These registers can only be written in special mode. ITST0 — Interrupt Test Register 0 ...

Page 144

... Freescale Semiconductor, Inc. Resets and Interrupts source of reset in a system. The POR circuit only initializes internal circuitry during cold starts and cannot be used to force a reset as system voltage drops important to use an external low voltage reset circuit (for example: MC34064 or MC33464) to prevent power transitions or corruption of RAM or EEPROM ...

Page 145

... Freescale Semiconductor, Inc. software failing to execute the sequence properly causes a COP reset to occur. In addition, windowed COP operation can be selected. In this mode, a write to the COPRST register must occur in the last 25% of the selected period. A premature write will also reset the part. 10.8.4 Clock Monitor Reset If clock frequency falls below a predetermined limit when the clock monitor is enabled, a reset occurs ...

Page 146

... Freescale Semiconductor, Inc. Resets and Interrupts 10.9.3 Interrupts PSEL is initialized in the HPRIO register with the value $F2, causing the external IRQ pin to have the highest I-bit interrupt priority. The IRQ pin is configured for level-sensitive operation (for wired-OR systems). However, the interrupt mask bits in the CPU12 CCR are set to mask X- and I-related interrupt requests ...

Page 147

... Freescale Semiconductor, Inc. 10.9.7 Other Resources The enhanced capture timer (ECT), pulse width modulation timer (PWM), serial communications interfaces (SCI0 and SCI1), serial peripheral interface (SPI), inter-IC bus (IIC), Motorola Scalable CANs (MSCAN0 and MSCAN1) and analog-to-digital converters (ATD0 and ATD1) are off after reset. ...

Page 148

... Freescale Semiconductor, Inc. Resets and Interrupts If another interrupt is pending at the end of an interrupt service routine, the register unstacking and restacking is bypassed and the vector of the interrupt is fetched. Technical Data 148 For More Information On This Product, Resets and Interrupts Go to: www.freescale.com MC68HC912DT128A — Rev 4.0 ...

Page 149

... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A 11.1 Contents 11.2 11.3 11.4 11.2 Introduction The offers 16 additional I/O ports with key wake-up capability. The key wake-up feature of the MC68HC912DT128A issues an interrupt that will wake up the CPU when the STOP or WAIT mode. Two ports are associated with the key wake-up function: port H and port J ...

Page 150

... Freescale Semiconductor, Inc. I/O Ports with Key Wake-up 11.3 Key Wake-up and port Registers PORTJ — Port J Register Bit 7 6 PORT PJ7 PJ6 KWU KWJ7 KWJ6 RESET Read and write anytime. PORTH — Port H Register Bit 7 6 PH7 PH6 KWU KWH7 ...

Page 151

... Freescale Semiconductor, Inc. DDRH — Port H Data Direction Register Bit 7 6 DDH7 DDH6 RESET Data direction register H is associated with port H and designates each pin as an input or output. Read and write anytime. DDRH[7:0] — Data Direction Port H KWIEJ — Key Wake-up Port J Interrupt Enable Register ...

Page 152

... Freescale Semiconductor, Inc. I/O Ports with Key Wake-up KWIFJ — Key Wake-up Port J Flag Register Bit 7 6 KWIFJ7 KWIFJ6 RESET Read and write anytime. Each flag is set by an active edge on its associated input pin. This could be a rising or falling edge based on the state of the KWPJ register. To clear the flag, write one to the corresponding bit in KWIFJ ...

Page 153

... Freescale Semiconductor, Inc. KWPJ — Key Wake-up Port J Polarity Register Bit 7 6 KWPJ7 KWPJ6 RESET Read and write anytime best to clear the flags after initializing this register because changing the polarity of a bit can cause the associated flag to become set. KWPJ[7:0] — Key Wake-up Port J Polarity Selects KWPH — ...

Page 154

... Freescale Semiconductor, Inc. I/O Ports with Key Wake-up 11.4 Key Wake-Up Input Filter The KWU input signals are filtered by a digital filter which is active only during STOP mode. The purpose of the filter is to prevent single pulses shorter than a specified value from waking the part from STOP. ...

Page 155

... Freescale Semiconductor, Inc. Glitch, filtered out, no STOP wake-up Valid STOP Wake-Up pulse t KWSTP Minimum time interval between pulses to be recognized as single pulses Figure 11-1. STOP Key Wake-up Filter MC68HC912DT128A — Rev 4.0 MOTOROLA For More Information On This Product, min. t max. KWSTP ...

Page 156

... Freescale Semiconductor, Inc. I/O Ports with Key Wake-up Technical Data 156 For More Information On This Product, I/O Ports with Key Wake-up Go to: www.freescale.com MC68HC912DT128A — Rev 4.0 MOTOROLA ...

Page 157

... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A 12.1 Contents 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 Real-Time Interrupt 186 12.11 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 12.12 Clock Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 12.2 Introduction Clock generation circuitry generates the internal and external E-clock signals as well as internal clock signals used by the CPU and on-chip peripherals ...

Page 158

... Freescale Semiconductor, Inc. Clock Functions 12.3 Clock Sources A compatible external clock signal can be applied to the EXTAL pin or the MCU can generate a clock signal using an on-chip oscillator circuit and an external crystal or ceramic resonator. The MCU uses several types of internal clock signals derived from the primary clock signal: TxCLK clocks are used by the CPU ...

Page 159

... Freescale Semiconductor, Inc. T1CLK T2CLK T3CLK T4CLK INT ECLK PCLK XCLK CANCLK Figure 12-1. Internal Clock Relationships 12.4 Phase-Locked Loop (PLL) The phase-locked loop (PLL) of the MC68HC912DT128A is designed for robust operation in an Automotive environment. The allowed PLL crystal or ceramic resonator reference of 0.5 to 8MHz is selected for the wide availability of components with good stability over the automotive temperature range ...

Page 160

... Freescale Semiconductor, Inc. Clock Functions EXTAL REDUCED CONSUMPTION OSCILLATOR XTAL EXTALi SLOW MODE SLWCLK PROGRAMMABLE CLOCK DIVIDER ÷2 SLDV <5:0> EXTALi Figure 12-2. PLL Functional Diagram The PLL may be used to run the MCU from a different time base than the incoming crystal value. It creates an integer multiple of a reference frequency. For increased flexibility, the crystal clock can be divided by values in a range of 1 – ...

Page 161

... Freescale Semiconductor, Inc. 12.5 Acquisition and Tracking Modes The lock detector compares the frequencies of the VCO feedback clock, DIVCLK, and the final reference clock, REFCLK. Therefore, the speed of the lock detector is directly proportional to the final reference frequency. The circuit determines the mode of the PLL and the lock condition based on this comparison ...

Page 162

... Freescale Semiconductor, Inc. Clock Functions for the base clock. See the source for the base clock and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application. The following conditions apply when the PLL is in automatic bandwidth control mode: • ...

Page 163

... Freescale Semiconductor, Inc. 12.6 Limp-Home and Fast STOP Recovery modes If the crystal frequency is not available due to a crystal failure or a long crystal start-up time, the MCU system clock can be supplied by the VCO at its minimum operating frequency, f called Limp-Home Mode and is only available when the VDDPLL supply voltage is at VDD level (i ...

Page 164

... Freescale Semiconductor, Inc. Clock Functions VCO clock at its minimum frequency, f clock, allowing the MCU to continue operating. The MCU is said to be operating in “limp-home” mode with the forced VCO clock as the system clock. PLLON and BCSP (‘bus clock select PLL’) signals are forced high and the MCS (‘module clock select’) signal is forced low ...

Page 165

... Freescale Semiconductor, Inc. values before the clock loss. All clocks return to their normal settings and Clock Monitor control is returned to the CME & FCME bits. If AUTO and BCSP bits were set before the clock loss (selecting the PLL to provide a system clock) the SYSCLK ramps-up and the PLL locks at the previously selected frequency ...

Page 166

... Freescale Semiconductor, Inc. Clock Functions 12.6.2 No Clock at Power-On Reset The voltage level on VDDPLL determines how the MCU responds to an external clock loss in this case. With the VDDPLL supply voltage at VDD level, any reset sets the Clock Monitor Enable bit (CME) and the PLLON bit and clears the NOLHM bit. ...

Page 167

... Freescale Semiconductor, Inc. During this power up sequence, after the POR pulse falling edge, the VCO supplies the limp-home clock frequency to the 13-stage counter, as the BCSP output is forced high and MCS is forced low. XCLK, BCLK and MCLK are forced to be PCLK, which is supplied by the VCO at f The initial period taken for the 13-stage counter to reach 4096 defines the internal reset period ...

Page 168

... Freescale Semiconductor, Inc. Clock Functions 12.6.3 STOP Exit and Fast STOP Recovery Stop mode is entered when a STOP instruction is executed. Recovery from STOP depends primarily on the state of the three status bits NOLHM, CME & DLY. The DLY bit controls the duration of the waiting period between the actual exit for some key blocks (e ...

Page 169

... Freescale Semiconductor, Inc. 12.6.4 STOP exit without Limp Home mode, clock monitor disabled (NOLHM=1, CME=0, DLY=X) If Limp home mode is disabled (V CME (or FCME) bit is cleared, the MCU goes into STOP mode when a STOP instruction is executed. If EXTALi clock is present then exit from STOP will occur normally using this clock ...

Page 170

... Freescale Semiconductor, Inc. Clock Functions Where the crystal start-up time is longer than the initial count of 4096 XCLK cycles the absence of an external clock, the MCU recovers from STOP following the 4096 count in limp-home mode with both the LHOME flag set and the LHIF limp-home interrupt request set to indicate it is not operating at the desired frequency ...

Page 171

... Freescale Semiconductor, Inc. Each time the 13-stage counter reaches a count of 4096 XCLK cycles (every 8192 cycles), a check of the clock monitor status is performed. If the clock monitor indicates the presence of an external clock limp-home mode is de-asserted, the LHOME flag is cleared and the limp-home interrupt flag is set ...

Page 172

... Freescale Semiconductor, Inc. Clock Functions 12.6.9 Pseudo-STOP exit in Limp Home mode with Delay (NOLHM=0, CME=X, DLY=1) When coming out of Pseudo-STOP mode with the NOLHM bit cleared and the DLY bit set, the MCU goes into limp-home mode (regardless of the state of the CME or FCME bits). ...

Page 173

... Freescale Semiconductor, Inc. 12.6.11 Pseudo-STOP exit without Limp Home mode, clock monitor enabled (NOLHM=1, CME=1, DLY=X) If the NOLHM bit is set and the CME (or FCME) bits are set, a clock monitor failure is detected when a STOP instruction is executed and the MCU resets via the clock monitor reset vector. ...

Page 174

... Freescale Semiconductor, Inc. Clock Functions . . Table 12-1. Summary of STOP Mode Exit Conditions Mode STOP exit without Limp Home mode, clock monitor disabled Executing the STOP instruction without Limp Home mode, clock monitor enabled STOP exit in Limp Home mode with Delay STOP exit in Limp Home mode ...

Page 175

... Freescale Semiconductor, Inc. 12.6.14 PLL Register Descriptions Bit RESET SYNR — Synthesizer Register Read anytime, write anytime, except when BCSP = 1 (PLL selected as bus clock). If the PLL is on, the count in the loop divider (SYNR) register effectively multiplies up the bus frequency from the PLL reference frequency by SYNR + 1 ...

Page 176

... Freescale Semiconductor, Inc. Clock Functions Bit 7 6 LOCKIF LOCK RESET PLLFLG — PLL Flags Read anytime, refer to each bit for write conditions. LOCKIF — PLL Lock Interrupt Flag change in LOCK bit LOCK condition has changed, either from a locked state clear the flag, write one to this bit in PLLFLG. Cleared in limp-home mode. LOCK — ...

Page 177

... Freescale Semiconductor, Inc. Bit 7 6 LOCKIE PLLON RESET: 0 (1) — PLLCR — PLL Control Register 1. Set when VDDPLL power supply is high. Forced to 0 when VDDPLL is low. 2. Cleared when VDDPLL power supply is high. Forced to 1 when VDDPLL is low. Read and write anytime. Exceptions are listed below for each bit. ...

Page 178

... Freescale Semiconductor, Inc. Clock Functions ACQ — Not in Acquisition If AUTO = 1 (ACQ is Read Only PLL VCO is not within the desired tolerance of the target 1 = After the phase lock loop circuit is turned on, indicates the PLL If AUTO = High bandwidth PLL loop selected 1 = Low bandwidth PLL loop selected PSTP — ...

Page 179

... Freescale Semiconductor, Inc. Bit BCSP RESET CLKSEL — Clock Generator Clock select Register Read and write anytime. Exceptions are listed below for each bit. BCSP and BCSS bits determine the clock used by the main system including the CPU and buses. BCSP — Bus Clock Select PLL 0 = SYSCLK is derived from the crystal clock or from SLWCLK ...

Page 180

... Freescale Semiconductor, Inc. Clock Functions Bit RESET SLOW — Slow mode Divider Register Read and write anytime. A write to this register changes the SLWCLK frequency with minimum delay (less than one SLWCLK cycle), thus allowing immediate tune the performance versus power consumption for the modules using this clock ...

Page 181

... Freescale Semiconductor, Inc. 12.7 System Clock Frequency Formulae See Figure SLWCLK = EXTALi / ( 2 x SLOW ) SLWCLK = EXTALi PLLCLK = 2 x EXTALi x (SYNR + 1) / (REFDV + 1) ECLK = SYSCLK / 2 XCLK = SLWCLK / 2 PCLK = SYSCLK / 2 BCLK Boolean equations: SYSCLK = (BCSP & PLLCLK) | (BCSP & BCSS & EXTALi) | (BCSP & ...

Page 182

... Freescale Semiconductor, Inc. Clock Functions 12.8 Clock Divider Chains Figure clock divider chains for the various peripherals on the MC68HC912DT128A. BCSP BCSS PHASE PLLCLK LOCK LOOP EXTALi EXTAL REDUCED EXTALi CONSUMPTION OSCILLATOR XTAL EXTALi SLOW MODE SLWCLK CLOCK DIVIDER Figure 12-6. Clock Generation Chain ...

Page 183

... Freescale Semiconductor, Inc. Bus clock select bits BCSP and BCSS in the clock select register (CLKSEL) determine which clock drives SYSCLK for the main system including the CPU and buses. BCSS has no effect if BCSP is set. During the transition, the clock select output will be held low and all CPU activity will cease until the transition is complete ...

Page 184

... Freescale Semiconductor, Inc. Clock Functions MCLK REGISTER: TMSK2 BITS: PR2, PR1, PR0 TEN 0:0:0 ÷ 0:0:1 2 ÷ 0:1:0 2 ÷ 0:1:1 2 ÷ 1:0:0 2 ÷ 1:0:1 2 ÷ 1:1:0 2 ÷ 1:1:1 2 PORT T7 PAEN Technical Data 184 For More Information On This Product, REGISTER: MCCTL BITS: MCPR1, MCPR0 ...

Page 185

... Freescale Semiconductor, Inc. PCLK 5-BIT MODULUS COUNTER (PR0-PR4) ÷ 2 REGISTER: SP0BR BITS: SPR2, SPR1, SPR0 0:0:0 ÷ 2 0:0:1 ÷ 0:1:0 2 ÷ 2 0:1:1 ÷ 2 1:0:0 ÷ 2 1:0:1 ÷ 2 1:1:0 ÷ 2 1:1:1 Figure 12-9. Clock Chain for MSCAN, SPI, ATD0, ATD1 and BDM 12 ...

Page 186

... Freescale Semiconductor, Inc. Clock Functions In addition, windowed COP operation can be selected. In this mode, writes to the COPRST register must occur in the last 25% of the selected period. A premature write will also reset the part. 12.10 Real-Time Interrupt There is a real time (periodic) interrupt available to the user. This interrupt will occur at one of seven selected rates ...

Page 187

... Freescale Semiconductor, Inc. 12.12 Clock Function Registers All register addresses shown reflect the reset state. Registers may be mapped to any 2K byte space. Bit 7 6 RTIE RSWAI RESET RTICTL — Real-Time Interrupt Control Register RTIE — Real Time Interrupt Enable Read and write anytime. ...

Page 188

... Freescale Semiconductor, Inc. Clock Functions RTR2, RTR1, RTR0 — Real-Time Interrupt Rate Select Read and write anytime. Rate select for real-time interrupt. The clock used for this module is the XCLK. Table 12-4. Real Time Interrupt Rates RTR2 RTR1 RTR0 Divide X By: ...

Page 189

... Freescale Semiconductor, Inc. Bit 7 6 CME FCME RESET: 0/1 0 RESET: 0/1 0 COPCTL — COP Control Register CME — Clock Monitor Enable Read and write anytime. If FCME is set, this bit has no meaning nor effect Clock monitor is disabled. Slow clocks and stop instruction may ...

Page 190

... Freescale Semiconductor, Inc. Clock Functions FCMCOP — Force Clock Monitor Reset or COP Watchdog Reset Writes are not allowed in normal modes, anytime in special modes. Read anytime. If DISR is set, this bit has no effect Normal operation clock monitor failure reset or a COP failure reset is forced WCOP — ...

Page 191

... Freescale Semiconductor, Inc. Divide CR2 CR1 CR0 XCLK OFF 1.048576 ms -0/+1.024 Time for writing $55 following previous COP restart of time-out logic due to writing $AA. 2. Please refer to WCOP bit description above. 3. Window COP cannot be used at this rate. DISR — Disable Resets from COP Watchdog and Clock Monitor Writes are not allowed in normal modes, anytime in special modes ...

Page 192

... Freescale Semiconductor, Inc. Clock Functions Bit 7 6 Bit 7 6 RESET COPRST — Arm/Reset COP Timer Register Always reads $00. Writing $55 to this address is the first step of the COP watchdog sequence. Writing $AA to this address is the second step of the COP watchdog sequence. Other instructions may be executed between these writes but both must be completed in the correct order prior to time-out to avoid a watchdog reset ...

Page 193

... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A 13.1 Contents 13.2 13.3 13.4 13.5 13.2 Introduction The oscillator implementation on the original 0.65µ (non-suffix) HC12 D- family is a ‘Colpitts Oscillator with Translated Ground’. This design was carried over to the first 0.5µ devices (A-suffix the 0L05H mask set, and is described in Section Specification ...

Page 194

... Freescale Semiconductor, Inc. Oscillator mask set. This implementation, described in section MC68HC912Dx128P Pierce Oscillator Automatic Level Control circuit to provide a lower power oscillator than traditional Pierce oscillators based on simple inverter circuits. In this section of the document, the term MC68HC912Dx128P refers only to the MC68HC912DT128P and MC68HC912DG128P devices. ...

Page 195

... Freescale Semiconductor, Inc. Figure 13-1. MC68HC912DT128A Colpitts Oscillator Architecture MC68HC912DT128A — Rev 4.0 MOTOROLA For More Information On This Product, MC68HC912DT128A Oscillator Specification - OTA CFLT + 2 RFLT - ALC + RFLT CFLT RESD EXTAL Resonator Oscillator Go to: www.freescale.com Oscillator BUF BIAS EN GM XTAL C X-EX C X-VSS ...

Page 196

... Freescale Semiconductor, Inc. Oscillator 13.3.2 MC68HC912DT128A Oscillator Design Guidelines Proper and robust operation of the oscillator circuit requires excellent board layout design practice. Poor layout of the application board can contribute to EMC susceptibility, noise generation, slow starting oscillators, and reaction to noise on the clock input buffer. In addition to published errata for the MC68HC912DT128A, the following guidelines must be followed or failure in operation may occur ...

Page 197

... Freescale Semiconductor, Inc. NOTE: EXTAL and XTAL routing resistances are less important than capacitances. Using minimum width traces is an acceptable trade-off to reduce capacitance. 13.4 MC68HC912Dx128C Colpitts Oscillator Specification This section applies to the 1L05H mask set, which refers to the newest set of CGM improvements (to the MC68HC912DT128A) with the Colpitts oscillator configuration enabled ...

Page 198

... Freescale Semiconductor, Inc. Oscillator Figure 13-2. MC68HC912Dx128C Colpitts Oscillator Architecture There are the following primary differences between the previous (’A’) and new (’C’) Colpitts oscillator configurations: • • Technical Data 198 For More Information On This Product, CFLT 2 RFLT RFLT ...

Page 199

... Freescale Semiconductor, Inc. • • 13.4.1.1 Clock Buffer Hysteresis The input clock buffer uses an Operational Transconductance Amplifier (labeled ‘OTA’ in the figure above) followed by a digital buffer to amplify the input signal on the EXTAL pin into a full-swing clock for use by the clock generation section of the microcontroller. There is an internal R-C filter (composed of components RFLT2 and CFLT2 in the figure above), which creates the DC value to which the EXTAL signal is compared ...

Page 200

... Freescale Semiconductor, Inc. Oscillator 13.4.1.2 Internal Parasitic Reduction Any oscillator circuit’s gain margin is reduced when a low AC-impedance (low resistance or high capacitance) is placed in parallel with the resonator. In the Colpitts oscillator configuration, this impedance is dominated by the parasitic capacitance from the EXTAL pin to VSS. ...

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