MC912DG128ACPV Freescale Semiconductor, MC912DG128ACPV Datasheet - Page 111

• Manufacturer Part Number: MC912DG128ACPV
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128ACPV

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PUCR — Pull-Up Control Register
MC68HC912DT128A — Rev 4.0
MOTOROLA
RESET:
PUPK
Bit 7
0
PUPJ
6
0
CALE — Calibration Reference Enable
DBENE — DBE or Inverted E Clock on PE7
PUPK — Pull-Up Port K Enable
Read and write anytime.
Normal modes: write once. Special modes: write anytime EXCEPT
the first time. Read anytime.
DBENE controls which signal is output on PE7 when NDBE control bit
is cleared. The inverted E clock output can be used to latch the
address for de-multiplexing. It has the same behavior as the E clock,
except it is inverted. Please note that in the case of idle expansion
bus, the ‘not E clock’ signal could stay high for many cycles.
The DBENE bit has no effect in Single Chip or Peripheral Modes and
PE7 is defaulted to the CAL function if CALE bit is set in PEAR
register or to an I/O otherwise.
These bits select pull-up resistors for any pin in the corresponding
port that is currently configured as an input. This register is not in the
map in peripheral mode.
Read and write anytime.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = Calibration reference is disabled and PE7 is general purpose
1 = Calibration reference is enabled on PE7 in single chip and
0 = PE7 pin used for DBE external control of data enable on
1 = PE7 pin used for inverted E clock output in expanded modes
0 = Port K pull-ups are disabled.
1 = Enable pull-up devices for all port K input pins.
PUPH
5
0
I/O in single chip or peripheral modes or if NDBE bit is set.
peripheral modes or if NDBE bit is set.
memories in expanded modes when NDBE = 0
when NDBE = 0
Bus Control and Input/Output
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PUPE
4
1
3
0
0
2
0
0
PUPB
Bus Control and Input/Output
1
0
PUPA
Bit 0
0
Technical Data
Registers
$000C
111