SI1005-C-GM Silicon Laboratories Inc, SI1005-C-GM Datasheet
SI1005-C-GM
Specifications of SI1005-C-GM
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SI1005-C-GM Summary of contents
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Ultra Low Power: 0.9 to 3.6 V Operation - Typical sleep mode current < 0.1 µA; retains state and RAM contents over full supply range; fast wakeup of < 2 µs Less than 600 nA with RTC running - Less ...
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Si1000/1/2/3/4/5 2 Rev. 1.0 ...
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Table of Contents 1. System Overview ..................................................................................................... 16 1.1. Typical Connection Diagram ............................................................................. 20 1.2. CIP-51™ Microcontroller Core .......................................................................... 21 1.3. Port Input/Output ............................................................................................... 22 1.4. Serial Ports ........................................................................................................ 23 1.5. Programmable Counter Array............................................................................ 23 1.6. 10-bit SAR ADC with ...
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Si1000/1/2/3/4/5 8.3. Instruction Set.................................................................................................. 110 8.4. CIP-51 Register Descriptions .......................................................................... 115 9. Memory Organization ............................................................................................ 118 9.1. Program Memory............................................................................................. 119 9.2. Data Memory ................................................................................................... 119 10. On-Chip XRAM ..................................................................................................... 121 10.1. Accessing XRAM........................................................................................... 121 10.2. Special Function Registers............................................................................ 122 11. ...
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Selecting the Optimum Switch Size............................................................... 169 16.7. DC-DC Converter Clocking Options .............................................................. 169 16.8. DC-DC Converter Behavior in Sleep Mode ................................................... 169 16.9. DC-DC Converter Register Descriptions ....................................................... 171 16.10. DC-DC Converter Specifications ................................................................. 173 17. Voltage Regulator (VREG0)................................................................................. ...
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Si1000/1/2/3/4/5 23.6. Data Handling and Packet Handler ............................................................... 261 23.7. RX Modem Configuration .............................................................................. 269 23.8. Auxiliary Functions ........................................................................................ 269 23.9. Reference Design.......................................................................................... 280 23.10. Application Notes and Reference Designs .................................................. 283 23.11. Customer Support ....................................................................................... 283 23.12. Register Table ...
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List of Registers SFR Definition 5.1. ADC0CN: ADC0 Control ................................................................ 81 SFR Definition 5.2. ADC0CF: ADC0 Configuration ...................................................... 82 SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration ................................. 83 SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time ............................ 84 SFR ...
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Si1000/1/2/3/4/5 SFR Definition 15.2. CRC0IN: CRC0 Data Input ........................................................ 162 SFR Definition 15.3. CRC0DAT: CRC0 Data Output .................................................. 162 SFR Definition 15.4. CRC0AUTO: CRC0 Automatic Control ...................................... 163 SFR Definition 15.5. CRC0CNT: CRC0 Automatic Flash Sector Count ..................... 163 SFR ...
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SFR Definition 22.1. SPI1CFG: SPI Configuration ..................................................... 234 SFR Definition 22.2. SPI1CN: SPI Control ................................................................. 235 SFR Definition 22.3. SPI1CKR: SPI Clock Rate ......................................................... 236 SFR Definition 22.4. SPI1DAT: SPI Data ................................................................... 237 SFR Definition 24.1. SMB0CF: SMBus Clock/Configuration ...................................... ...
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... Figure 1.3. Si1002 Block Diagram ........................................................................... 18 Figure 1.4. Si1003 Block Diagram ........................................................................... 18 Figure 1.5. Si1004 Block Diagram ........................................................................... 19 Figure 1.6. Si1005 Block Diagram ........................................................................... 19 Figure 1.7. Si1002/3 RX/TX Direct-tie Application Example .................................... 20 Figure 1.8. Si1000/1 Antenna Diversity Application Example ................................. 20 Figure 1.9. Port I/O Functional Block Diagram ........................................................ 22 Figure 1 ...
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Figure 7.3. Comparator Hysteresis Plot ................................................................ 101 Figure 7.4. CPn Multiplexer Block Diagram ........................................................... 106 Figure 8.1. CIP-51 Block Diagram ......................................................................... 109 Figure 9.1. Si1000/1/2/3/4/5 Memory Map ............................................................ 118 Figure 9.2. Flash Program Memory Map ............................................................... 119 Figure 13.1. Flash ...
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Si1000/1/2/3/4/5 Figure 23.17. Operation of Data Whitening, Manchester Encoding, and CRC ..... 266 Figure 23.18. Manchester Coding Example .......................................................... 266 Figure 23.19. Header ............................................................................................. 268 Figure 23.20. POR Glitch Parameters ................................................................... 269 Figure 23.21. General Purpose ADC Architecture ................................................ 272 ...
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Figure 27.8. Timer 3 8-Bit Mode Block Diagram. .................................................. 347 Figure 27.9. Timer 3 Capture Mode Block Diagram .............................................. 348 Figure 28.1. PCA Block Diagram ........................................................................... 352 Figure 28.2. PCA Counter/Timer Block Diagram ................................................... 353 Figure 28.3. PCA Interrupt Block ...
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Si1000/1/2/3/4/5 List of Tables Table 2.1. Product Selection Guide ......................................................................... 27 Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 .................................................. 28 Table 3.2. QFN-42 Package Dimensions ................................................................ 35 Table 3.3. PCB Land Pattern ................................................................................... 39 Table 4.1. Absolute Maximum Ratings .................................................................... ...
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Table 21.3. Port I/O Assignment for External Digital Event Capture Functions .... 211 Table 22.1. Serial Interface Timing Parameters .................................................... 230 Table 22.2. SPI Timing Parameters ...................................................................... 238 Table 23.1. EZRadioPRO Operating Modes ......................................................... 240 Table 23.2. EZRadioPRO Operating Modes ...
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Si1000/1/2/3/4/5 1. System Overview Si1000/1/2/3/4/5 devices are fully integrated mixed-signal system-on-a-chip MCUs. Highlighted features are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers. ® 240–960 MHz EZRadioPRO transceiver Single/Dual battery operation with ...
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CIP-51 8051 Power On Controller Core Reset/PMU 64k Byte ISP Flash Wake Program Memory Reset 256 Byte SRAM Debug / C2CK/RST Programming 4096 Byte XRAM Hardware C2D CRC Engine VDD VREG SYSCLK GND Precision 24.5 MHz Oscillator Low Power 20 ...
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Si1000/1/2/3/4/5 CIP-51 8051 Power On Controller Core Reset/PMU 64k Byte ISP Flash Wake Program Memory Reset 256 Byte SRAM Debug / C2CK/RST Programming 4096 Byte XRAM Hardware C2D VDD VREG GND Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator ...
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... VBAT Low Power Converter 20 MHz Oscillator GND External XTAL1 Oscillator XTAL2 Circuit XTAL3 SmaRTClock Oscillator XTAL4 System Clock Configuration Figure 1.6. Si1005 Block Diagram Si1000/1/2/3/4/5 Analog Peripherals RF XCVR (240-960 MHz) 6-bit IREF0 IREF PA External Internal VREF VREF AGC VDD VREF A 10-bit ...
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Si1000/1/2/3/4/5 1.1. Typical Connection Diagram The application shown in Figure 1.7 is designed for a system with a TX/RX direct-tie configuration without the use of a TX/RX switch. Most lower power applications will use this configuration. A complete direct-tie reference ...
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CIP-51™ Microcontroller Core 1.2.1. Fully 8051 Compatible The Si1000/1/2/3/4/5 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The ...
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Si1000/1/2/3/4/5 1.3. Port Input/Output Digital and analog resources are available through 19 (Si1000/1/2/ (Si1004/5) I/O pins. Three addi- tional GPIO pins are available through the EZRadioPRO peripheral. Port pins are organized as three byte- wide ports. Port pins ...
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Serial Ports The Si1000/1/2/3/4/5 family includes an SMBus/I configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. There ...
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Si1000/1/2/3/4/5 1.6. 10-bit SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode Si1000/1/2/3/4/5 devices have a 300 ksps, 10-bit successive-approximation-register (SAR) ADC with inte- grated track-and-hold and programmable window detector. ADC0 also has an autonomous low power ...
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P0.0 P2.6* Temp Sensor Digital Supply VDD_MCU *P1.0 – P1.4 are not available as device pins Figure 1.12. ADC0 Multiplexer Block Diagram 1.7. Programmable Current Reference (IREF0) Si1000/1/2/3/4/5 devices include an on-chip programmable current reference (source or sink) with two ...
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Si1000/1/2/3/4/5 CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 Analog Input Multiplexer Px.x CP0 + Px.x Px.x CP0 - Px.x Figure 1.13. Comparator 0 Functional Block Diagram CP1EN CP1OUT CP1RIF CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 Analog Input Multiplexer Px.x CP1 ...
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... Ordering Information Table 2.1. Product Selection Guide Si1000-C- 4352 P Si1001-C- 4352 P Si1002-C- 4352 P Si1003-C- 4352 P Si1004-C- 4352 P Si1005-C- 4352 Rev. 1.0 Si1000/1/2/3/4/5 +20 dBm 1.8 P QFN-42 +20 dBm 1.8 P QFN-42 +13 dBm 1.8 P QFN-42 +13 dBm 1.8 P QFN-42 +13 dBm 0.9 P QFN-42 +13 dBm 0.9 P QFN-42 27 ...
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Si1000/1/2/3/4/5 3. Pinout and Package Definitions Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 Name Pin Number Si1000/1 Si1004/5 Si1002/3 VDD_MCU 38 — GND_MCU 37 — — VBAT 41 GND — 38 VBAT- DCEN — 40 VDD_MCU / — 39 DC+ ...
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Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 (Continued) Name Pin Number Type Si1000/1 Si1004/5 Si1002/3 RST I/O C2CK D I/O P2. I/O C2D D I/O XTAL3 XTAL4 ...
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Si1000/1/2/3/4/5 Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 (Continued) Name Pin Number Si1000/1 Si1004/5 Si1002 CNVSTR P0 IREF0 ...
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Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 (Continued) Name Pin Number Type Si1000/1 Si1004/5 Si1002/3 GPIO_0 I I/O GPIO_1 I I/O GPIO_2 I I/O nIRQ ...
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Si1000/1/2/3/4/5 XTAL3 1 P2.5 2 P2.4 3 P2.3 4 P2.2 5 P2.1 6 P2.0 7 P1 P1.5 nIRQ 11 XOUT 12 XIN 13 N.C. 14 Figure 3.1. Si1000/1/2/3 Pinout Diagram (Top View) 32 GND_MCU Si1000/1/2/3 Top ...
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P2.7/C2D 1 XTAL4 2 XTAL3 3 P2.3 4 P2.2 5 P2.1 6 P2.0 7 P1.7 8 P1.6 9 P1.5 10 nIRQ 11 XOUT 12 XIN 13 N.C. 14 Figure 3.2. Si1004/5 Pinout Diagram (Top View) Si1000/1/2/3/4/5 GND_M CU Si1004/5 Top ...
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Si1000/1/2/3/4/5 Figure 3.3. QFN-42 Package Drawing 34 Rev. 1.0 ...
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Table 3.2. QFN-42 Package Dimensions Dimension Min Typ Max A 0.60 0.65 0.70 b 0.20 0.25 0.30 D 5.00 BSC D1 3.00 BSC D2 4.25 BSC D3 3.11 3.16 3.21 D4 2.68 2.73 2.78 e 0.50 BSC E 7.00 BSC ...
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Si1000/1/2/3/4/5 Figure 3.4. Typical QFN-42 Landing Diagram 36 Rev. 1.0 ...
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Figure 3.5. VIA Placement and Keepout Region Si1000/1/2/3/4/5 Rev. 1.0 37 ...
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Si1000/1/2/3/4/5 Figure 3.6. Typical PCB Stencil Diagram 38 Rev. 1.0 ...
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Dimension C1 X1 (27x) Y1 (27x (15x) Y2 (15x General All dimensions shown are in millimeters (mm) unless otherwise noted. 1. This land pattern design is based on ...
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Si1000/1/2/3/4/5 4. Electrical Characteristics In sections 4.1 and 4.2, , “V ” refers to the VDD_MCU supply voltage on Si1000/1/2/3 devices and to the DD VDD_MCU/DC+ supply voltage on Si1004/5 devices. The ADC, Comparator, and Port I/O specifications in these ...
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MCU Electrical Characteristics Table 4.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed ...
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Si1000/1/2/3/4/5 Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this ...
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Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this table. ...
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Si1000/1/2/3/4/5 Table 4.2. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the ‘F9xx" for details on how to achieve the supply current specifications listed in this ...
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F < 10 MHz 4100 4000 Oneshot Enabled 3900 3800 3700 3600 3500 3400 3300 3200 3100 3000 2900 2800 2700 2600 2500 2400 2300 2200 2100 2000 1900 1800 1700 1600 1500 1400 240 µA/MHz 1300 1200 1100 ...
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Si1000/1/2/3/4/5 4200 4100 4000 3900 3800 3700 3600 3500 3400 3300 3200 3100 3000 2900 2800 2700 2600 2500 2400 2300 2200 2100 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 ...
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Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC Si1000/1/2/3/4/5 Load Current (mA) Rev. 1.0 47 ...
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Si1000/1/2/3/4/5 Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC Load current (mA) Rev. 1.0 ...
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Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC Si1000/1/2/3/4/5 Load current (mA) Rev. 1.0 49 ...
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Si1000/1/2/3/4/5 Figure 4.6. Typical One-Cell Suspend Mode Current 50 Rev. 1.0 ...
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Table 4.3. Port I/O DC Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters Output High Voltage High Drive Strength, PnDRV IOH = –3 mA, Port I/O push-pull IOH = ...
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Si1000/1/2/3/4/5 3.6 3.3 3 2.7 2.4 2.1 1.8 1.5 1.2 0 3.6 3.3 3 2.7 2.4 2.1 1.8 1.5 1.2 0 Figure 4.7. Typical VOH Curves, 1.8–3 Typical VOH (High Drive Mode) ...
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Typical VOH (High Drive Mode) 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0 Load Current (mA) Typical VOH (Low Drive Mode) 1.8 1.7 1.6 1.5 1.4 ...
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Si1000/1/2/3/4/5 1.8 1.5 1.2 0.9 0.6 0.3 0 -80 -70 1.8 1.5 1.2 0.9 0.6 0 Figure 4.9. Typical VOL Curves, 1.8–3 Typical VOL (High Drive Mode) VDD = 3.6V VDD = 3.0V VDD ...
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Typical VOL (High Drive Mode) 1.8 1.5 1.2 0.9 0.6 0.3 0 -80 -70 -60 -50 -40 -30 Load Current (mA) Typical VOL (Low Drive Mode) 1.8 1.5 1.2 0.9 0.6 0 ...
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Si1000/1/2/3/4/5 0.5 0.4 0.3 0.2 0 0.5 0.4 0.3 VDD = 1.8V 0.2 VDD = 1.5V VDD = 1.2V 0.1 VDD = 0. Figure 4.11. Typical VOL Curves, 0.9–1 Typical VOL (High Drive ...
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Table 4.4. Reset Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameter RST Output Low Voltage RST Input High Voltage RST Input Low Voltage RST Input Pullup Current VDD_MCU Monitor Threshold (V ...
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Si1000/1/2/3/4/5 Table 4.5. Power Management Electrical Specifications V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameter Idle Mode Wake-up Time Suspend Mode Wake-up Time Sleep Mode Wake-up Time Table 4.6. Flash Electrical Characteristics V ...
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Table 4.7. Internal Precision Oscillator Electrical Characteristics V = 1 –40 to +85 °C unless otherwise specified; Using factory-calibrated settings Parameter Oscillator Frequency Oscillator Supply Current 25 °C; includes bias current (from ...
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Si1000/1/2/3/4/5 Table 4.9. ADC0 Electrical Characteristics V = 1.8 to 3.6V V, VREF = 1.65 V (REFSL[1:0] = 11), DD Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Dynamic performance (10 kHz sine-wave single-ended input, ...
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Table 4.10. Temperature Sensor Electrical Characteristics V = 1 +85 °C unless otherwise specified. – DD Parameter Linearity Slope 1 Slope Error Offset 1 Offset Error Temperature Sensor Settling 2 Time Supply Current Notes: 1. ...
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Si1000/1/2/3/4/5 Table 4.12. IREF0 Electrical Characteristics V = 1 +85 °C, unless otherwise specified. – DD Parameter Static Performance Resolution Output Compliance Range High Current Mode, Source Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale ...
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Table 4.13. Comparator Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise noted. DD Parameter Response Time: * Mode 2 1 Response Time: * Mode 1, ...
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Si1000/1/2/3/4/5 Table 4.13. Comparator Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise noted. DD Parameter Hysteresis Mode 0 Hysteresis 1 Hysteresis 2 Hysteresis 3 Hysteresis 4 Mode 1 Hysteresis 1 Hysteresis 2 Hysteresis 3 ...
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Table 4.14. DC-DC Converter (DC0) Electrical Characteristics –40 to +85 °C unless otherwise specified. VBAT = 0.9 to 1.8 V, Parameter Input Voltage Range Input Inductor Value Input Inductor Current Rating Inductor DC Resistance Input Capacitor Value Output Voltage Range ...
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Si1000/1/2/3/4/5 ® 4.3. EZRadioPRO Electrical Characteristics Table 4.16. DC Characteristics Parameter Symbol Supply Voltage V DD Range Power Saving Modes I Shutdown I Low Power Digital Regulator ON (Register Standby I Sleep (Register values retained) and Main Digital I Sensor- ...
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Table 4.17. Synthesizer AC Electrical Characteristics Parameter Symbol Synthesizer Frequency F SYN Range Synthesizer Frequency F RES-LB 2 Resolution F RES-HB Reference Frequency f REF_LV 2 Input Level 2 Synthesizer Settling Time t LOCK 2 F Residual FM RMS 2 ...
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Si1000/1/2/3/4/5 Table 4.18. Receiver AC Electrical Characteristics Parameter Symbol RX Frequence Range Sensitivity P RX_2 P RX_40 P RX_100 P RX_125 P RX_OOK 3 RX Channel Bandwidth BW BER Variation vs Power P RX_RES 3 Level ...
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Table 4.19. Transmitter AC Electrical Characteristics Parameter Symbol TX Frequency Range FSK Data Rate DR FSK 2 OOK Data Rate DR OOK Modulation Deviation Δf1 Δf2 Modulation Deviation Δf RES 2 Resolution Output Power Range— P ...
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Si1000/1/2/3/4/5 Table 4.20. Auxiliary Block Specifications Parameter Symbol Temperature Sensor Accuracy Temperature Sensor Sensitivity Low Battery Detector LBD 2 Resolution Low Battery Detector LBD 2 Conversion Time Microcontroller Clock ...
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Table 4.21. Digital IO Specifications (nIRQ) Parameter Symbol Rise Time T RISE Fall Time T FALL Input Capacitance C IN Logic High Level Input V IH Voltage Logic Low Level Input V IL Voltage Input Current I IN Logic High ...
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Si1000/1/2/3/4/5 Table 4.23. Absolute Maximum Ratings Parameter V to GND DD Instantaneous V to GND on TX Output Pin RF-peak Sustained V to GND on TX Output Pin RF-peak Voltage on Digital Control Inputs Voltage on Analog Inputs RX Input ...
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Definition of Test Conditions for the EZRadioPRO Peripheral Production Test Conditions +25 °C +3.3 VDC DD Sensitivity measured at 919 MHz TX output power measured at 915 MHz External reference ...
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Si1000/1/2/3/4/5 5. 10-Bit SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode The ADC0 on the Si1000/1/2/3/4 300 ksps, 10-bit successive-approximation-register (SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 also has an autonomous ...
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Input Voltage Right-Justified ADC0H:ADC0L (AD0SJST = 000) VREF x 1023/1024 0x03FF VREF x 512/1024 0x0200 VREF x 256/1024 0x0100 0 0x0000 When the repeat count is greater than 1, the output conversion code represents the accumulated result of the conversions ...
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Si1000/1/2/3/4/5 5.2. Modes of Operation ADC0 has a maximum conversion speed of 300 ksps. The ADC0 conversion clock (SARCLK divided version of the system clock when Burst Mode is disabled (BURSTEN = 0 divided version of ...
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Tracking Modes Each ADC0 conversion must be preceded by a minimum tracking time in order for the converted result to be accurate. The minimum tracking time is given in Table 4.9. The AD0TM bit in register ADC0CN controls the ...
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Si1000/1/2/3/4/5 5.2.3. Burst Mode Burst Mode is a power saving feature that allows ADC0 to remain in a low power state between conver- sions. When Burst Mode is enabled, ADC0 wakes from a low power state, accumulates ...
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Settling Time Requirements A minimum amount of tracking time is required before each conversion can be performed, to allow the sampling capacitor voltage to settle. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, any ...
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Si1000/1/2/3/4/5 5.2.5. Gain Setting The ADC has gain settings of 1x and 0.5x mode, the full scale reading of the ADC is determined directly 0.5x mode, the full-scale reading of the ADC occurs when ...
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SFR Definition 5.1. ADC0CN: ADC0 Control Bit 7 6 AD0EN BURSTEN AD0INT Name R/W R/W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xE8; bit-addressable; Bit Name 7 AD0EN ADC0 Enable. 0: ADC0 Disabled (low-power shutdown). 1: ...
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Si1000/1/2/3/4/5 SFR Definition 5.2. ADC0CF: ADC0 Configuration Bit 7 6 AD0SC[4:0] Name Type 1 1 Reset SFR Page = 0x0; SFR Address = 0xBC Bit Name 7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Divider. SAR Conversion clock is derived from FCLK ...
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SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration Bit 7 6 Name Reserved AD0AE R/W W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xBA Bit Name 7 Reserved Read = 0b. 6 AD0AE ADC0 Accumulate Enable. Enables ...
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Si1000/1/2/3/4/5 SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time Bit 7 6 Name Reserved R R Type 0 0 Reset SFR Page = 0xF; SFR Address = 0xBA Bit Name 7 Reserved Read = 0b; Must write 0b. 6:4 ...
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SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time Bit 7 6 Name R R Type 0 0 Reset SFR Page = 0xF; SFR Address = 0xBD Bit Name 7:6 Unused Read = 00b; Write = Don’t Care. 5:0 AD0TK[5:0] ...
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Si1000/1/2/3/4/5 SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte Bit 7 6 Name Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xBE Bit Name Description 7:0 ADC0[15:8] ADC0 Data Word High Byte. Note: If Accumulator shifting ...
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Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space ...
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Si1000/1/2/3/4/5 SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte Bit 7 6 Name Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xC6 Bit Name 7:0 AD0LT[15:8] ADC0 Less-Than High Byte. Most Significant Byte of the 16-bit Less-Than ...
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ADC0H:ADC0L Input Voltage (Px.x - GND) VREF x (1023/1024) 0x03FF AD0WINT not affected 0x0081 VREF x (128/1024) 0x0080 ADC0LTH:ADC0LTL 0x007F 0x0041 VREF x (64/1024) 0x0040 ADC0GTH:ADC0GTL 0x003F AD0WINT not affected 0x0000 0 Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended ...
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Si1000/1/2/3/4/5 5.5. ADC0 Analog Multiplexer ADC0 on Si1000/1/2/3/4/5 has an analog multiplexer, referred to as AMUX0. AMUX0 selects the positive inputs to the single-ended ADC0. Any of the following may be selected as the positive input: Port I/O pins, the ...
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SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select Bit 7 6 Name R R Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xBB Bit Name 7:5 Unused Read = 000b; Write = Don’t Care. 4:0 AD0MX AMUX0 ...
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Si1000/1/2/3/4/5 5.6. Temperature Sensor An on-chip temperature sensor is included on the Si1000/1/2/3/4/5 which can be directly accessed via the ADC multiplexer in single-ended configuration. To use the ADC to measure the temperature sensor, the ADC mux channel should select ...
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Figure 5.9 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C. Parame- ters that affect ADC measurement, in particular the voltage reference value, will also affect temper- ature measurement. A single-point offset measurement of the temperature ...
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Si1000/1/2/3/4/5 SFR Definition 5.13. TOFFH: ADC0 Data Word High Byte Bit 7 6 Name R R Type Varies Varies Varies Reset SFR Page = 0xF; SFR Address = 0x86 Bit Name 7:0 TOFF[9:2] Temperature Sensor Offset High Bits. Most Significant ...
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Voltage and Ground Reference Options The voltage reference MUX is configurable to use an externally connected voltage reference, one of two internal voltage references, or one of two power supply voltages (see Figure 5.10). The ground reference MUX allows ...
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Si1000/1/2/3/4/5 5.9. Internal Voltage References For applications requiring the maximum number of port I/O pins, or very short VREF turn-on time, the 1.65 V high-speed reference will be the best internal reference option to choose. The high speed internal reference ...
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SFR Definition 5.15. REF0CN: Voltage Reference Control Bit 7 6 REFGND Name R R Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xD1 Bit Name 7:6 Unused Read = 00b; Write = Don’t Care. 5 REFGND Analog ...
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Si1000/1/2/3/4/5 6. Programmable Current Reference (IREF0) Si1000/1/2/3/4/5 devices include an on-chip programmable current reference (source or sink) with two out- put current settings: Low Power Mode and High Current Mode. The maximum current output in Low Power Mode is 63 ...
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Comparators Si1000/1/2/3/4/5 devices include two on-chip programmable voltage comparators: Comparator 0 (CPT0) is shown in Figure 7.1; Comparator 1 (CPT1) is shown in Figure 7.2. The two comparators operate identi- cally, but may differ in their ability to be ...
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Si1000/1/2/3/4/5 7.2. Comparator Outputs When a comparator is enabled, its output is a logic 1 if the voltage at the positive input is higher than the voltage at the negative input. When disabled, the comparator output is a logic 0. ...
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Comparator Response Time Comparator response time may be configured in software via the CPTnMD registers described on “CPT0MD: Comparator 0 Mode Selection” on page 103 and “CPT1MD: Comparator 1 Mode Selection” on page 105. Four response time settings are ...
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Si1000/1/2/3/4/5 7.5. Comparator Register Descriptions The SFRs used to enable and configure the comparators are described in the following register descrip- tions. A Comparator must be enabled by setting the CPnEN bit to logic 1 before it can be used. ...
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SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection Bit 7 6 CP0RIE Name R/W R Type 1 0 Reset SFR Page = All Pages; SFR Address = 0x9D Bit Name 7 Reserved Read = 1b, Must Write 1b. 6 Unused ...
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Si1000/1/2/3/4/5 SFR Definition 7.3. CPT1CN: Comparator 1 Control Bit 7 6 CP1EN CP1OUT CP1RIF Name R/W R Type 0 0 Reset SFR Page= 0x0; SFR Address = 0x9A Bit Name 7 CP1EN Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 ...
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SFR Definition 7.4. CPT1MD: Comparator 1 Mode Selection Bit 7 6 CP1RIE Name R/W R Type 1 0 Reset SFR Page = 0x0; SFR Address = 0x9C Bit Name 7 Reserved Read = 1b, Must Write 1b. 6 Unused Read ...
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Si1000/1/2/3/4/5 7.6. Comparator0 and Comparator1 Analog Multiplexers Comparator0 and Comparator1 on Si1000/1/2/3/4/5 devices have analog input multiplexers to connect Port I/O pins and internal signals the comparator inputs; CP0+/CP0- are the positive and negative input multiplexers for Comparator0 and CP1+/CP1- ...
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SFR Definition 7.5. CPT0MX: Comparator0 Input Channel Select Bit 7 6 CMX0N[3:0] Name R/W R/W Type 1 1 Reset SFR Page = 0x0; SFR Address = 0x9F Bit Name 7:4 CMX0N Comparator0 Negative Input Selection. Selects the negative input channel ...
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Si1000/1/2/3/4/5 SFR Definition 7.6. CPT1MX: Comparator1 Input Channel Select Bit 7 6 CMX1N[3:0] Name R/W R/W Type 1 1 Reset SFR Page = 0x0; SFR Address = 0x9E Bit Name 7:4 CMX1N Comparator1 Negative Input Selection. Selects the negative input ...
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CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset ...
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Si1000/1/2/3/4/5 With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execu- tion ...
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Table 8.1. CIP-51 Instruction Set Summary Mnemonic Arithmetic Operations ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data Add immediate to A ADDC ...
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Si1000/1/2/3/4/5 Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement Rotate A left RLC A Rotate A left through Carry RR A Rotate ...
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Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic ANL C, bit AND direct bit to Carry ANL C, /bit AND complement of direct bit to Carry ORL C, bit OR direct bit to carry ORL C, /bit OR complement of ...
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Si1000/1/2/3/4/5 Notes on Registers, Operands and Addressing Modes Register R0–R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (twos complement) offset relative to the first ...
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CIP-51 Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic l. Future product versions may use these bits to implement new features in which ...
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Si1000/1/2/3/4/5 SFR Definition 8.3. SP: Stack Pointer Bit 7 6 Name Type 0 0 Reset SFR Page = All Pages; SFR Address = 0x81 Bit Name 7:0 SP[7:0] Stack Pointer. The Stack Pointer holds the location of the top of ...
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SFR Definition 8.6. PSW: Program Status Word Bit Name R/W R/W Type 0 0 Reset SFR Page = All Pages; SFR Address = 0xD0; Bit-Addressable Bit Name 7 CY Carry Flag. This bit is set when ...
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Si1000/1/2/3/4/5 9. Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space ...
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Program Memory The CIP-51 core has program memory space. The Si1000/1/2/3/4/5 implements 64 kB (Si1000/ (Si1001/3) of this program memory space as in-system, re-programmable Flash memory, orga- nized in a contiguous block from ...
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Si1000/1/2/3/4/5 direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the upper 128 bytes of data memory. Figure 9.1 illustrates the data memory organization of the Si1000/1/2/3/4/5. 9.2.1.1. General Purpose Registers The lower 32 bytes ...
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On-Chip XRAM The Si1000/1/2/3/4/5 MCUs include on-chip RAM mapped into the external data memory space (XRAM). The external memory space may be accessed using the external move instruction (MOVX) with the target address specified in either the data pointer ...
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Si1000/1/2/3/4/5 10.2. Special Function Registers The special function register used for configuring XRAM access is EMI0CN. SFR Definition 10.1. EMI0CN: External Memory Interface Control Bit 7 6 Name R R Type 0 0 Reset SFR Page = 0x0; SFR Address ...
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Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the Si1000/1/2/3/4/5's resources and peripher- als. The CIP-51 controller core duplicates the SFRs ...
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Si1000/1/2/3/4/5 11.1. SFR Paging To accommodate more than 128 SFRs in the 0x80 to 0xFF address space, SFR paging has been imple- mented. By default, all SFR accesses target SFR Page 0x0 to allow access to the registers listed in ...
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SFR Definition 11.1. SFRPage: SFR Page Bit 7 6 Name Type 0 0 Reset SFR Page = All Pages; SFR Address = 0xA7 Bit Name 7:0 SFRPAGE[7:0] SFR Page. Specifies the SFR Page used when reading, writing, or modifying special ...
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Si1000/1/2/3/4/5 Table 11.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address SFR Page CRC0IN 0x93 0xF DC0CF 0x96 0x0 DC0CN 0x97 0x0 DPH 0x83 All DPL 0x82 All EIE1 0xE6 ...
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Table 11.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address SFR Page PCA0CPH5 0xD3 0x0 PCA0CPL0 0xFB 0x0 PCA0CPL1 0xE9 0x0 PCA0CPL2 0xEB 0x0 PCA0CPL3 0xED 0x0 PCA0CPL4 0xFD 0x0 ...
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Si1000/1/2/3/4/5 Table 11.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address SFR Page TCON 0x88 0x0 TH0 0x8C 0x0 TH1 0x8D 0x0 TL0 0x8A 0x0 TL1 0x8B 0x0 TMOD 0x89 ...
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Interrupt Handler The Si1000/1/2/3/4/5 microcontroller family includes an extended interrupt system supporting multiple interrupt sources and two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of the ...
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Si1000/1/2/3/4/5 12.3. Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior- ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot ...
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Table 12.1. Interrupt Summary Interrupt Source Reset 0x0000 External Interrupt 0 (INT0) 0x0003 Timer 0 Overflow 0x000B External Interrupt 1 (INT1) 0x0013 Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B SmaRTClock Alarm 0x0043 ADC0 ...
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Si1000/1/2/3/4/5 Table 12.1. Interrupt Summary (Continued) Interrupt Source SmaRTClock Oscillator 0x008B Fail EZRadioPRO Serial 0x0093 Interface (SPI1) Notes: 1. Indicates a read-only interrupt pending flag. The interrupt enable may be used to prevent software from vectoring to the associated ...
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SFR Definition 12.1. IE: Interrupt Enable Bit ESPI0 Name R/W R/W Type 0 0 Reset SFR Page = All Pages; SFR Address = 0xA8; Bit-Addressable Bit Name 7 EA Enable All Interrupts. Globally enables/disables all interrupts. It ...
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Si1000/1/2/3/4/5 SFR Definition 12.2. IP: Interrupt Priority Bit 7 6 PSPI0 Name R R/W Type 1 0 Reset SFR Page = 0x0; SFR Address = 0xB8; Bit-Addressable Bit Name 7 Unused Read = 1b, Write = don't care. 6 PSPI0 ...
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SFR Definition 12.3. EIE1: Extended Interrupt Enable 1 Bit 7 6 ET3 ECP1 Name R/W R/W Type 0 0 Reset SFR Page = All Pages; SFR Address = 0xE6 Bit Name 7 ET3 Enable Timer 3 Interrupt. This bit sets ...
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Si1000/1/2/3/4/5 SFR Definition 12.4. EIP1: Extended Interrupt Priority 1 Bit 7 6 PT3 PCP1 Name R/W R/W Type 0 0 Reset SFR Page = All Pages; SFR Address = 0xF6 Bit Name 7 PT3 Timer 3 Interrupt Priority Control. This ...
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SFR Definition 12.5. EIE2: Extended Interrupt Enable 2 Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Page = All Pages;SFR Address = 0xE7 Bit Name 7:4 Unused Read = 0000b. Write = Don’t care. 3 ESPI1 Enable ...
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Si1000/1/2/3/4/5 SFR Definition 12.6. EIP2: Extended Interrupt Priority 2 Bit 7 6 Name R R Type 0 0 Reset SFR Page = All Pages; SFR Address = 0xF7 Bit Name 7:4 Unused Read = 0000b. Write = Don’t care. PSPI1 ...
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External Interrupts INT0 and INT1 The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active ...
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Si1000/1/2/3/4/5 SFR Definition 12.7. IT01CF: INT0/INT1 Configuration Bit 7 6 IN1PL IN1SL[2:0] Name R/W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xE4 Bit Name 7 IN1PL INT1 Polarity. 0: INT1 input is active low. 1: INT1 ...
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Flash Memory On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system through the C2 interface or by software using the MOVX write instruction. Once cleared to logic 0, ...
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Si1000/1/2/3/4/5 13.1.2. Flash Erase Procedure The Flash memory is organized in 1024-byte pages. The erase operation applies to an entire page (setting all bytes in the page to 0xFF). To erase an entire 1024-byte page, perform the following steps: 1. ...
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Non-volatile Data Storage The Flash memory can be used for non-volatile data storage as well as program code. This allows data such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX ...
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Si1000/1/2/3/4/5 The level of Flash security depends on the Flash access method. The three Flash access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware ...
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Determining the Device Part Number at Run Time In many applications, user software may need to determine the MCU part number at run time in order to determine the hardware capabilities. The part number can be determined by reading ...
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Si1000/1/2/3/4/5 5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, "RSTSRC = 0x02" is correct, but "RSTSRC |= ...
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Minimizing Flash Read Current The Flash memory in the Si1000/1/2/3/4/5 devices is responsible for a substantial portion of the total digital supply current when the device is executing code. Below are suggestions to minimize Flash read current. 1. Use ...
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Si1000/1/2/3/4/5 SFR Definition 13.1. PSCTL: Program Store R/W Control Bit 7 6 Name R R Type 0 0 Reset SFR Page =0x0; SFR Address = 0x8F Bit Name 7:3 Unused Read = 00000b, Write = don’t care. 2 SFLE Scratchpad ...
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SFR Definition 13.2. FLKEY: Flash Lock and Key Bit 7 6 Name Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xB6 Bit Name 7:0 FLKEY[7:0] Flash Lock and Key Register. Write: This register provides a lock and ...
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Si1000/1/2/3/4/5 SFR Definition 13.3. FLSCL: Flash Scale Bit 7 6 BYPASS Name R R/W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xB6 Bit Name 7 Reserved Always Write BYPASS Flash Read Timing One-Shot ...
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Power Management Si1000/1/2/3/4/5 devices support 5 power modes: Normal, Idle, Stop, Suspend, and Sleep. The power management unit (PMU0) allows the device to enter and wake-up from the available power modes. A brief description of each power mode is ...
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Si1000/1/2/3/4/5 14.1. Normal Mode The MCU is fully functional in Normal Mode. Figure 14.1 shows the on-chip power distribution to various peripherals. There are three supply voltages powering various sections of the chip: VBAT, VDD/DC+, and the 1.8 V internal ...
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Idle Mode Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon as the instruction that sets the bit completes execution. All internal registers and memory maintain their original ...
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Si1000/1/2/3/4/5 14.4. Suspend Mode Setting the Suspend Mode Select bit (PMU0CF.6) causes the system clock to be gated off and all internal oscillators disabled. All digital logic (timers, communication peripherals, interrupts, CPU, etc.) stops functioning until one of the enabled ...
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Note: By default, the VDD/DC+ supply is connected to VBAT upon entry into Sleep Mode (one-cell mode). If the VDDSLP bit (DC0CF.1) is set to logic 1, the VDD/DC+ supply will float in Sleep Mode. This allows the decoupling capacitance ...
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Si1000/1/2/3/4/5 SFR Definition 14.1. PMU0CF: Power Management Unit Configuration Bit 7 6 SLEEP SUSPEND CLEAR Name W W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xB5 Bit Name Description 7 SLEEP Sleep Mode Select 6 SUSPEND ...
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SFR Definition 14.2. PCON: Power Management Control Register Bit 7 6 Name Type 0 0 Reset SFR Page = All Pages; SFR Address = 0x87 Bit Name Description 7:2 GF[5:0] General Purpose Flags 1 STOP Stop Mode Select 0 IDLE ...
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Si1000/1/2/3/4/5 15. Cyclic Redundancy Check Unit (CRC0) Si1000/1/2/3/4/5 devices include a cyclic redundancy check unit (CRC0) that can perform a CRC using a 16-bit or 32-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register. CRC0 ...
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Create the CRC "dividend" for polynomial arithmetic (binary arithmetic // with no carries) CRC_acc = CRC_acc ^ (CRC_input << 8); // "Divide" the poly into the dividend using CRC XOR subtraction // CRC_acc holds the "remainder" of each divide ...
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Si1000/1/2/3/4/5 15.2. Preparing for a CRC Calculation To prepare CRC0 for a CRC calculation, software should select the desired polynomial and set the initial value of the result. Two polynomials are available: 0x1021 (16-bit) and 0x04C11DB7 (32-bit). The CRC0 result ...
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SFR Definition 15.1. CRC0CN: CRC0 Control Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Page = 0xF; SFR Address = 0x92 Bit Name 7:5 Unused Read = 000b; Write = Don’t Care. 4 CRC0SEL CRC0 Polynomial Select ...
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Si1000/1/2/3/4/5 SFR Definition 15.2. CRC0IN: CRC0 Data Input Bit 7 6 Name Type 0 0 Reset SFR Page = 0xF; SFR Address = 0x93 Bit Name 7:0 CRC0IN[7:0] CRC0 Data Input. Each write to CRC0IN results in the written data ...
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SFR Definition 15.4. CRC0AUTO: CRC0 Automatic Control Bit 7 6 AUTOEN CRCDONE Name Type 0 1 Reset SFR Page = 0xF; SFR Address = 0x96 Bit Name 7 AUTOEN Automatic CRC Calculation Enable. When AUTOEN is set to 1, any ...
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Si1000/1/2/3/4/5 15.5. CRC0 Bit Reverse Feature CRC0 includes hardware to reverse the bit order of each bit in a byte as shown in Figure 15.2. Each byte of data written to CRC0FLIP is read back bit reversed. For example, if ...
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On-Chip DC-DC Converter (DC0) Si1004/5 devices include an on-chip dc-dc converter to allow operation from a single cell battery with a supply voltage as low as 0.9 V. The dc-dc converter is a switching boost converter with an input ...
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Si1000/1/2/3/4/5 16.1. Startup Behavior On initial power-on, the dc-dc converter outputs a constant 50% duty cycle until there is sufficient voltage on the output capacitor to maintain regulation. The size of the output capacitor and the amount of load cur- ...
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High Power Applications The dc-dc converter is designed to provide the system with output power, however, it can safely provide up to 100 mW of output power without any risk of damage to the device. For ...
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Si1000/1/2/3/4/5 DC-DC Converter Enabled 0.9 to 1.8 V Supply Voltage (one-cell mode) DC-DC Converter Disabled 1.8 to 3.6 V Supply Voltage (two-cell mode) Figure 16.2. DC-DC Converter Configuration Options When the dc-dc converter “Enabled” configuration (one-cell mode) is ...
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When using the ADC with the dc-dc converter, we also recommend enabling the SYNC bit in the DC0CN register to minimize interference. These general guidelines provide the best performance in most applications, ...
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Si1000/1/2/3/4/5 from VBAT to ground when the VDD_MCU/DC+ level falls below VBAT, but this leakage current should be small compared to the current from VDD_MCU/DC+. The amount of time that it takes for a device configured in one-cell mode to ...
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DC-DC Converter Register Descriptions The SFRs used to configure the dc-dc converter are described in the following register descriptions. The reset values for these registers can be used as-is in most systems; therefore, no software intervention or initialization is ...
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Si1000/1/2/3/4/5 SFR Definition 16.2. DC0CF: DC-DC Converter Configuration Bit 7 6 Name Reserved CLKDIV[1:0] R R/W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0x96 Bit Name 7 Reserved Read = 0b; Must write 0b. 6:5 CLKDIV[1:0] ...
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DC-DC Converter Specifications See Table 4.14 on page 65 for a detailed listing of dc-dc converter specifications. Si1000/1/2/3/4/5 Rev. 1.0 173 ...
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Si1000/1/2/3/4/5 17. Voltage Regulator (VREG0) Si1000/1/2/3/4/5 devices include an internal voltage regulator (VREG0) to regulate the internal core supply to 1.8 V from a VDD_MCU supply of 1.8 to 3.6 V. Electrical characteristics for the on-chip regulator are specified in ...
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Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: CIP-51 halts program execution Special Function Registers (SFRs) are initialized to their defined ...
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Si1000/1/2/3/4/5 18.1. Power-On (VBAT Supply Monitor) Reset During power-up, the device is held in a reset state and the RST pin is driven low until additional delay occurs before the device is released from reset; the ...
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Power-Fail (VDD_MCU Supply Monitor) Reset Si1000/1/2/3/4/5 devices have a VDD_MCU Supply Monitor that is enabled and selected as a reset source after each power-on or power-fail reset. When enabled and selected as a reset source, any power down transition ...
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Si1000/1/2/3/4/5 Important Notes: The Power-on Reset (POR) delay is not incurred after a VDD_MCU supply monitor reset. See Section “4. Electrical Characteristics” on page 40 for complete electrical characteristics of the VDD_MCU monitor. Software should take care not to ...
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SFR Definition 18.1. VDM0CN: VDD_MCU Supply Monitor Control Bit 7 6 VDMEN VDDSTAT VDDOK Name R/W R Type 1 Varies Varies Reset SFR Page = 0x0; SFR Address = 0xFF Bit Name 7 VDMEN VDD_MCU Supply Monitor Enable. This bit ...
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Si1000/1/2/3/4/5 18.5. Comparator0 Reset Comparator0 can be configured as a reset source by writing the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on ...
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SFR Definition 18.2. RSTSRC: Reset Source Bit 7 6 RTC0RE FERROR C0RSEF Name R/W R Type Varies Varies Varies Reset SFR Page = 0x0; SFR Address = 0xEF. Bit Name Description 7 RTC0RE SmaRTClock Reset Enable and Flag 6 FERROR ...
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Si1000/1/2/3/4/5 19. Clocking Sources Si1000/1/2/3/4/5 devices include a programmable precision internal oscillator, an external oscillator drive circuit, a low power internal oscillator, and a SmaRTClock real time clock oscillator. The precision internal oscillator can be enabled/disabled and calibrated using the ...
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Programmable Precision Internal Oscillator All Si1000/1/2/3/4/5 devices include a programmable precision internal oscillator that may be selected as the system clock. OSCICL is factory calibrated to obtain a 24.5 MHz frequency. See Section “4. Electrical Characteristics” on page 40 ...
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Si1000/1/2/3/4 MHz 15 pF Figure 19.2. 25 MHz External Crystal Example Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible to the XTAL ...
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External RC Mode network is used as the external oscillator, the circuit should be configured as shown in Figure 19.1, Option 2. The RC network should be added to XTAL2, and XTAL2 should be configured for ...
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Si1000/1/2/3/4/5 3. Poll for XTLVLD > Switch the system clock to the external oscillator. 19.3.3. External Capacitor Mode If a capacitor is used as the external oscillator, the circuit should be configured as shown in Figure 19.1, Option ...
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Special Function Registers for Selecting and Configuring the System Clock The clocking sources on Si1000/1/2/3/4/5 devices are enabled and configured using the OSCICN, OSCICL, OSCXCN and the SmaRTClock internal registers. See Section “20. SmaRTClock (Real Time Clock)” on page ...
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Si1000/1/2/3/4/5 SFR Definition 19.2. OSCICN: Internal Oscillator Control Bit 7 6 IOSCEN IFRDY Name R/W R Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xB2 Bit Name 7 IOSCEN Internal Oscillator Enable. 0: Internal oscillator disabled. 1: ...
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SFR Definition 19.4. OSCXCN: External Oscillator Control Bit 7 6 Name XCLKVLD XOSCMD[2: Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xB1 Bit Name 7 XCLKVLD External Oscillator Valid Flag. Provides External Oscillator status and ...
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Si1000/1/2/3/4/5 20. SmaRTClock (Real Time Clock) Si1000/1/2/3/4/5 devices include an ultra low power 32-bit SmaRTClock Peripheral (Real Time Clock) with alarm. The SmaRTClock has a dedicated 32 kHz oscillator that can be configured for use with or without a crystal. ...
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Table 20.1. SmaRTClock Internal Registers SmaRTClock SmaRTClock Register Name Address Register 0x00–0x03 CAPTUREn SmaRTClock Capture Registers 0x04 RTC0CN SmaRTClock Control Register 0x05 RTC0XCN SmaRTClock Oscillator Control Register 0x06 RTC0XCF SmaRTClock Oscillator Configuration Register 0x07 RTC0PIN SmaRTClock Pin Configuration Register 0x08–0x0B ...
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Si1000/1/2/3/4/5 20.1.1. SmaRTClock Lock and Key Functions The SmaRTClock Interface is protected with a lock and key function. The SmaRTClock Lock and Key Reg- ister (RTC0KEY) must be written with the correct key codes, in sequence, before writes and reads ...
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Recommended Instruction Timing for a single register write with short strobe enabled: mov RTC0ADR, #095h mov RTC0DAT, #000h nop 20.1.4. SmaRTClock Interface Autoread Feature When Autoread is enabled, each read from RTC0DAT initiates the next indirect read operation on the ...
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Si1000/1/2/3/4/5 SFR Definition 20.1. RTC0KEY: SmaRTClock Lock and Key Bit 7 6 Name Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xAE Bit Name 7:0 RTC0ST SmaRTClock Interface Lock/Key and Status. Locks/unlocks the SmaRTClock interface when written. ...
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SFR Definition 20.2. RTC0ADR: SmaRTClock Address Bit 7 6 BUSY AUTORD Name R/W R/W Type 0 0 Reset SFR Page = 0x0; SFR Address = 0xAC Bit Name 7 BUSY SmaRTClock Interface Busy Indicator. Indicates SmaRTClock interface status. Writing 1 ...
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Si1000/1/2/3/4/5 SFR Definition 20.3. RTC0DAT: SmaRTClock Data Bit 7 6 Name Type 0 0 Reset SFR Page= 0x0; SFR Address = 0xAD Bit Name 7:0 RTC0DAT SmaRTClock Data Bits. Holds data transferred to/from the internal SmaRTClock register selected by RTC0ADR. ...
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SmaRTClock Clocking Sources The SmaRTClock peripheral is clocked from its own timebase, independent of the system clock. The SmaRTClock timebase is derived from the SmaRTClock oscillator circuit, which has two modes of opera- tion: Crystal Mode, and Self-Oscillate Mode. ...
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Si1000/1/2/3/4/5 20.2.3. Programmable Load Capacitance The programmable load capacitance has 16 values to support crystal oscillators with a wide range of rec- ommended load capacitance. If Automatic Load Capacitance Stepping is enabled, the crystal load capaci- tors start at the ...
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Automatic Gain Control (Crystal Mode Only) and SmaRTClock Bias Doubling Automatic Gain Control allows the SmaRTClock oscillator to trim the oscillation amplitude of a crystal in order to achieve the lowest possible power consumption. Automatic Gain Control automatically detects ...
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Si1000/1/2/3/4/5 . Table 20.3. SmaRTClock Bias Settings Mode Crystal Self-Oscillate 20.2.5. Missing SmaRTClock Detector The missing SmaRTClock detector is a one-shot circuit enabled by setting MCLKEN (RTC0CN. When the SmaRTClock Missing Clock Detector is enabled, OSCFAIL (RTC0CN.5) is ...