SI1005-C-GM Silicon Laboratories Inc, SI1005-C-GM Datasheet - Page 301

• Manufacturer Part Number: SI1005-C-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1005-C-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 0.9 V ~ 1.8 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Memory Size: 32kB Flash, 4kB RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 13 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4.1 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 4352 B
• Supply Current (max): 4.1 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1875-5

24.4.5. Data Register
The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been
received. Software may safely read or write to the data register when the SI flag is set. Software should not
attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0,
as the interface may be in the process of shifting a byte of data into or out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received
data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously
being shifted in. SMB0DAT always contains the last data byte present on the bus. In the event of lost arbi-
tration, the transition from master transmitter to slave receiver is made with the correct data or address in
SMB0DAT.
SFR Definition 24.5. SMB0DAT: SMBus Data
SFR Page = 0x0; SFR Address = 0xC2
Name
Reset
Bit
7
Type
Bit
:
0 SMB0DAT[7:0] SMBus Data.
Name
7
0
The SMB0DAT register contains a byte of data to be transmitted on the SMBus
serial interface or a byte that has just been received on the SMBus serial interface.
The CPU can read from or write to this register whenever the SI serial interrupt flag
(SMB0CN.0) is set to logic 1. The serial data in the register remains stable as long
as the SI flag is set. When the SI flag is not set, the system may be in the process
of shifting data in/out and the CPU should not attempt to access this register.
6
0
5
0
Rev. 1.0
SMB0DAT[7:0]
4
0
R/W
Function
3
0
Si1000/1/2/3/4/5
2
0
1
0
0
0
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