SI1005-C-GM Silicon Laboratories Inc, SI1005-C-GM Datasheet - Page 284

• Manufacturer Part Number: SI1005-C-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1005-C-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 0.9 V ~ 1.8 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Memory Size: 32kB Flash, 4kB RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 13 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4.1 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 4352 B
• Supply Current (max): 4.1 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1875-5

Add
0A
0B
0C
0D
0E
0F
1A
1B
1C
1D
1E
1F
2A
2B
2C
2D
2E
2F
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
R/W
R/W
R/W
R/W
R/W
R/W
R/W Microcontroller Output Clock
R/W
R/W
R/W
R/W
R/W
R/W ADC Sensor Amplifier Offset
R/W Temperature Sensor Control
R/W
R/W
R/W
R/W
R/W Low-Duty Cycle Mode Dura-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
Si1000/1/2/3/4/5
23.12. Register Table and Descriptions
284
Antenna Diversity Register 1
Antenna Diversity Register 2
Operating & Function Con-
Operating & Function Con-
AFC Loop Gearshift Over-
Temperature Value Offset
Received Signal Strength
RSSI Threshold for Clear
Wake-Up Timer Period 1
Wake-Up Timer Period 2
Wake-Up Timer Period 3
Wake-Up Timer Value 1
Wake-Up Timer Value 2
Crystal Oscillator Load
I/O Port Configuration
AFC Correction Read
OOK Counter Value 1
OOK Counter Value 2
Low Battery Detector
Battery Voltage Level
GPIO0 Configuration
GPIO1 Configuration
GPIO2 Configuration
AFC Timing Control
Oversampling Ratio
Timing Loop Gain 1
Timing Loop Gain 0
ADC Configuration
IF Filter Bandwidth
Gearshift Override
Interrupt Enable 1
Interrupt Enable 2
Interrupt Status 1
Interrupt Status 2
Slicer Peak Hold
Clock Recovery
Clock Recovery
Clock Recovery
Clock Recovery
Clock Recovery
Clock Recovery
Clock Recovery
Function/Desc
Device Version
Device Status
Device Type
Capacitance
AFC Limiter
ADC Value
Threshold
Indicator
Indicator
Channel
Offset 2
Offset 1
Offset 0
trol 1
trol 2
tion
ride
Table 23.9. EZRadioPRO Internal Register Descriptions
swait_timer[1]
dwn3_bypass
adcstart/ adc-
gpio0drv[1]
gpio1drv[1]
gpio2drv[1]
afc_corr[9]
afc_corr[9]
tsrange[1]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
adrssi1[7]
adrssib[7]
Reserved
ookcnt[7]
rxosr[10]
ncoff[15]
crgain[7]
Afclim[7]
enswdet
antdiv[2]
tvoffs[7]
wtm[15]
rssith[7]
rxosr[7]
ncoff[7]
xtalshft
wtv[15]
wtm[7]
iswdet
enfferr
adc[7]
swres
wtv[7]
rssi[7]
ldc[7]
afcbd
done
ffovfl
ifferr
D7
0
0
0
swait_timer[0]
gpio0drv[0]
gpio1drv[0]
gpio2drv[0]
afc_corr[8]
afc_corr[9]
enpreaval
tsrange[0]
entxffafull
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
adrssia[6]
adrssib[6]
adcsel[2]
ookcnt[6]
ncoff[14]
crgain[6]
Afclim[6]
antdiv[1]
extitst[2]
attack[2]
ipreaval
tvoffs[6]
wtm[14]
ndec[2]
rssith[6]
itxffafull
rxosr[6]
rxosr[9]
ncoff[6]
wtv[14]
wtm[6]
adc[6]
wtv[6]
rssi[6]
enlbd
ldc[6]
enafc
xlc[6]
ffunfl
D6
0
0
0
enpreainval
afcgearh[2]
afc_corr[7]
ipreainval
entxffaem
Reserved
Reserved
Reserved
Reserved
adrssia[5]
adrssib[5]
adcsel[1]
ookcnt[5]
Rev. 1.0
antdiv[0]
ncoff[13]
crgain[5]
Afclim[5]
ookfrzen
attack[1]
extitst[1]
ndec[1]
shwait[2]
crfast[2]
itxffaem
entsoffs
tvoffs[5]
wtm[13]
rssith[5]
rxosr[5]
rxosr[8]
ncoff[5]
wtv[13]
wtm[5]
rxffem
adc[5]
rssi[5]
clkt[1]
wtv[5]
xlc[5]
ldc[5]
enwt
pup0
pup1
pup2
D5
0
0
0
Reserved
afcgearh[1]
rxncocomp
afc_corr[6]
peakdeten
enrxffafull
Reserved
adrssia[4]
adrssib[4]
ookcnt[4]
adcsel[0]
crgain[4]
extitst[0]
shwait[1]
ncoff[12]
Afclim[4]
attack[0]
headerr
gpio0[4]
gpio1[4]
gpio2[4]
entstrim
tvoffs[4]
wtm[12]
ndec[0]
crfast[1]
rssith[4]
irxffafull
x32ksel
rxosr[4]
wtv[12]
stallctrl
ncoff[4]
wtm[4]
vbat[4]
rxmpk
adc[4]
enrssi
clkt[0]
wtv[4]
lbdt[4]
rssi[4]
wtr[4]
ldc[4]
xlc[4]
vc[4]
dt[4]
irssi
D4
Data
afcgearh[0]
afc_corr[5]
adcoffs[3]
adrssia[3]
adrssib[3]
ookcnt[3]
reserved
adcref[1]
ncoff[19]
crgain2x
crgain[3]
Afclim[3]
madeten
decay[3]
shwait[0]
ncoff[11]
gpio0[3]
gpio1[3]
gpio2[3]
tstrim[3]
tvoffs[3]
crfast[0]
rssith[3]
wtm[11]
rxosr[3]
ncoff[3]
wtv[11]
wtm[3]
vbat[3]
filset[3]
autotx
adc[3]
enwut
wtv[3]
lbdt[3]
rssi[3]
enext
xlc[3]
wtr[3]
ldc[3]
vc[3]
enlfc
itsdo
dt[3]
txon
iwut
iext
D3
1p5 bypass
afc_corr[4]
ookcnt[10]
adcoffs[2]
crgain[10]
adrssia[2]
adrssib[2]
enpksent
ookcnt[2]
reserved
adcref[0]
crslow[2]
anwait[2]
ncoff[18]
ncoff[10]
crgain[2]
Afclim[2]
decay[2]
gpio0[2]
gpio1[2]
gpio2[2]
tstrim[2]
tvoffs[2]
wtm[10]
rssith[2]
ipksent
mclk[2]
wtv[10]
rxosr[2]
ncoff[2]
vbat[2]
wtm[2]
filset[2]
enldm
adc[2]
wtv[2]
lbdt[2]
rssi[2]
enlbd
wtr[2]
xlc[2]
ldc[2]
vc[2]
dt[2]
rxon
dio2
ilbd
D2
afc_corr[3]
adcgain[1]
enchiprdy
adrssia[1]
adrssib[1]
enpkvalid
adcoffs[1]
ookcnt[9]
ookcnt[1]
crslow[1]
ncoff[17]
crgain[9]
crgain[1]
Afclim[1]
decay[1]
anwait[1]
ichiprdy
gpio0[1]
gpio1[1]
gpio2[1]
tstrim[1]
tvoffs[1]
rssith[1]
ipkvalid
rxosr[1]
ncoff[9]
ncoff[1]
mclk[1]
wtm[9]
wtm[1]
vbat[1]
filset[1]
adc[1]
lbdt[1]
matap
cps[1]
wtv[9]
wtv[1]
rssi[1]
ffclrrx
wtr[1]
ldc[1]
xlc[1]
vc[1]
pllon
dt[1]
dio1
D1
afc_corr[2]
encrcerror
adcgain[0]
adcoffs[0]
adrssia[0]
adrssib[0]
ookcnt[8]
ookcnt[0]
crslow[0]
crgain[8]
crgain[0]
Afclim[0]
icrcerror
anwait[0]
ncoff[16]
decay[0]
gpio0[0]
gpio1[0]
gpio2[0]
tstrim[0]
tvoffs[0]
rssith[0]
ph0size
rxosr[0]
mclk[0]
ncoff[8]
ncoff[0]
wtm[8]
wtm[0]
vbat[0]
filset[0]
cps[0]
enpor
adc[0]
wtv[8]
wtv[0]
lbdt[0]
rssi[0]
ffclrtx
wtr[0]
ldc[0]
xlc[0]
vc[0]
dt[0]
xton
dio0
ipor
D0
Default
00111
POR
BCh
0Ah
AEh
8Fh
1Eh
06h
00h
03h
01h
00h
7Fh
06h
00h
00h
00h
00h
00h
00h
20h
00h
03h
00h
01h
00h
14h
01h
40h
03h
64h
01h
47h
02h
00h
00h
18h
26h
—
—
—
—
—
—
—
—
—
—