SI1005-C-GM Silicon Laboratories Inc, SI1005-C-GM Datasheet - Page 179

• Manufacturer Part Number: SI1005-C-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1005-C-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 0.9 V ~ 1.8 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Memory Size: 32kB Flash, 4kB RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 13 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4.1 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 4352 B
• Supply Current (max): 4.1 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1875-5

SFR Definition 18.1. VDM0CN: VDD_MCU Supply Monitor Control
SFR Page = 0x0; SFR Address = 0xFF
18.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 4.4 for complete RST pin spec-
ifications. The external reset remains functional even when the device is in the low power Suspend and
Sleep Modes. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
18.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; otherwise,
this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it.
The missing clock detector reset is automatically disabled when the device is in the low power Suspend or
Sleep mode. Upon exit from either low power state, the enabled/disabled state of this reset source is
restored to its previous value. The state of the RST pin is unaffected by this reset.
Name
Reset
Bit
4:2
1:0
Type
7
6
5
Bit
VDDSTAT
Reserved
VDMEN
VDDOK
Unused
VDMEN
Name
R/W
7
1
VDDSTAT
VDD_MCU Supply Monitor Enable.
This bit turns the VDD_MCU supply monitor circuit on/off. The VDD_MCU Supply
Monitor cannot generate system resets until it is also selected as a reset source in
register RSTSRC (SFR Definition 18.2).
0: VDD_MCU Supply Monitor Disabled.
1: VDD_MCU Supply Monitor Enabled.
VDD_MCU Supply Status.
This bit indicates the current power supply status.
0: VDD_MCU is at or below the V
1: VDD_MCU is above the V
VDD_MCU Supply Status (Early Warning).
This bit indicates the current power supply status.
0: VDD_MCU is at or below the V
1: VDD_MCU is above the V
Read = 000b. Must Write 000b.
Read = 00b. Write = Don’t Care.
Varies
R
6
VDDOK
Varies
R
5
Reserved
R/W
Rev. 1.0
4
0
RST
WARN
threshold.
RST
WARN
monitor threshold.
Reserved
Function
threshold.
R/W
3
0
threshold.
Reserved
Si1000/1/2/3/4/5
R/W
2
0
R/W
1
0
R/W
0
0
179