SI1005-C-GM Silicon Laboratories Inc, SI1005-C-GM Datasheet - Page 300

• Manufacturer Part Number: SI1005-C-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1005-C-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 0.9 V ~ 1.8 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Memory Size: 32kB Flash, 4kB RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 13 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4.1 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 4352 B
• Supply Current (max): 4.1 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1875-5

Si1000/1/2/3/4/5
Workarounds :
A code example demonstrating these workarounds can be found in the SMBus examples folder with the
following default location:
C:\SiLabs\MCU\Examples\C8051F93x_92x\SMBus\F93x_SMBus_Slave_Multibyte_HWACK.c
The SMBus examples folder, along with examples for many additional peripherals, is created when the Sil-
icon Laboratories IDE is installed. The latest version of the IDE may be downloaded from the software
downloads page
The following issue is present when operating as a master in a multi-master SMBus configuration:
If the SMBus master loses arbitration in a multi-master system, it may cause interference on the SMBus by
driving SDA low during the ACK cycle of transfers which it is not participating. This will occur regardless of
the state of the ACK bit (SMB0CN.1).
Impact :
The SMBus master and slave participating in the transfer are prevented from generating a NACK by the
MCU because it is holding SDA low during the ACK cycle. There is a potential for the SMBus to lock up.
Workaround :
Disable Hardware Acknowledge (EHACK = 0) when the MCU is operating as a master in a multi-master
SMBus configuration.
300
a. The SMBus interrupt service routine should verify an address when it is received and clear SI as
b. Detection of Initial Start:
c. Schedule a timer interrupt to clear the ACK bit at an interval shorter than 7 bit periods when the
soon as possible if the address does not match to minimize clock stretching. To prevent clock
stretching when not being addressed, enable setup and hold time extensions (EXTHOLD = 1).

To distinguish between the reception of an address byte at the beginning of a transfer versus
the reception of a data byte when setup and hold time extensions are enabled (EXTHOLD = 1),
software should maintain a status bit to determine whether it is currently inside or outside a
transfer. Once hardware detects a matching slave address and interrupts the MCU, software
should assume a start condition and set the software bit to indicate that it is currently inside a
transfer. A transfer ends any time the STO bit is set or on an error condition (e.g., SCL Low
Timeout).

Detection of Repeated Start:

To detect the reception of an address byte in the middle of a transfer when setup and hold time
extensions are enabled (EXTHOLD = 1), disable setup and hold time extensions (EXTHOLD =
0) upon entry into a transfer and re-enable setup and hold time extensions (EXHOLD = 1) at the
end of a transfer.
slave is not being addressed. For example, on a 400 kHz SMBus, the ACK bit should be cleared
every 17.5 µs (or at 1/7 the bus frequency, 57 kHz). As soon as a matching slave address is
detected (a transfer is started), the timer which clears the ACK bit should be stopped and its
interrupt flag cleared. The timer should be re-started once a stop or error condition is detected
(the transfer has ended).
www.silabs.com/MCUDownloads

Rev. 1.0
on the Silicon Laboratories website.