SI1005-C-GM Silicon Laboratories Inc, SI1005-C-GM Datasheet - Page 145

• Manufacturer Part Number: SI1005-C-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1005-C-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 0.9 V ~ 1.8 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Memory Size: 32kB Flash, 4kB RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 13 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4.1 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 4352 B
• Supply Current (max): 4.1 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1875-5

13.4. Determining the Device Part Number at Run Time
In many applications, user software may need to determine the MCU part number at run time in order to
determine the hardware capabilities. The part number can be determined by reading the value of the Flash
byte at address 0xFFFE.

The value of the Flash byte at address 0xFFFE can be decoded as follows:

0xD0—Si1000
0xD1—Si1001
0xD2—Si1002
0xD3—Si1003
13.5. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of VDD, system clock frequency, or temperature. This accidental execution of Flash modi-
fying code can result in alteration of Flash memory contents causing a system failure that is only recover-
able by re-Flashing the code in the device.
To help prevent the accidental modification of Flash by firmware, the VDD Monitor must be enabled and
enabled as a reset source on C8051F92x-C8051F93x devices for the Flash to be successfully modified. If
either the VDD Monitor or the VDD Monitor reset source is not enabled, a Flash Error Device Reset
will be generated when the firmware attempts to modify the Flash.
The following guidelines are recommended for any system that contains routines which write or erase
Flash from code.
13.5.1. VDD Maintenance and the VDD Monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection
2. Make certain that the minimum V
3. Keep the on-chip VDD Monitor enabled and enable the V
Notes: On Si1000/1/2/3/4/5 devices, both the V
4. As an added precaution, explicitly enable the V
devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings
table are not exceeded.
this rise time specification, then add an external VDD brownout circuit to the RST pin of the device that
holds the device in reset until V
V
as possible. This should be the first set of instructions executed after the Reset Vector. For C-based
systems, this will involve modifying the startup code added by the C compiler. See your compiler
documentation for more details. Make certain that there are no delays in software between enabling the
V
found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories website.
source inside the functions that write and erase Flash memory. The V
should be placed just after the instruction to set PSWE to a 1, but before the Flash write or erase
operation instruction.
DD
DD
or erase Flash without generating a Flash Error Device Reset.

On Si1000/1/2/3/4/5 devices, both the V
after a power-on reset.
drops below the minimum device operating voltage.
Monitor and enabling the V
DD
DD
DD
reaches the minimum device operating voltage and re-asserts RST if
Monitor as a reset source. Code examples showing this can be
rise time specification of 1 ms is met. If the system cannot meet
DD
DD
Monitor and the V
Monitor and the V
Rev. 1.0
DD
Monitor and enable the V
DD
DD
DD
Monitor as a reset source as early in code
Monitor reset source are enabled by hardware
Monitor reset source must be enabled to write
Si1000/1/2/3/4/5
DD
Monitor enable instructions
DD
Monitor as a reset
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