DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 145

• Manufacturer Part Number: DK-DEV-5M570ZN
• Description: KIT DEV MAX V 5M570Z
• Manufacturer: Altera
• Series: MAX® Vr
• Type: CPLDr

Specifications of DK-DEV-5M570ZN

• Contents: Board, Cable(s), Software and Documentation
• Silicon Manufacturer: Altera
• Core Architecture: CPLD
• Core Sub-architecture: MAX
• Silicon Core Number: 5M
• Silicon Family Name: MAX V
• Kit Contents: MAX V CPLD Development Board, USB Cable
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: 5M570ZF256
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2722

Chapter 7: User Flash Memory in MAX V Devices
Simulation Parameters
Simulation Parameters
Document Revision History
Table 7–17. Document Revision History
January 2011 Altera Corporation
January 2011
December 2010
Date
Padding Data into Memory Map
The ALTUFM_I2C megafunction uses the upper 8 bits of the UFM 16-bit word;
therefore, the 8 least significant bits should be padded with 1s, as shown in
Figure
Figure 7–41. Padding Data into Memory Map
In the ALTUFM megafunction, you have an option to simulate the OSC output port at
the maximum or the minimum frequency during the design simulation. The
frequency chosen is only used as the timing parameter for the Quartus II simulator
and does not affect the real MAX V device OSC output frequency.
Table 7–17
Version
1.1
1.0
7–41.
lists the revision history for this chapter.
1
Updated
Initial release.
0
8-bit valid data to be placed
in the upper byte
1
“Oscillator”
0
1
0
section.
1
0
1
Changes
Pad the lower byte with eight '1's
1
1
1
1
1
MAX V Device Handbook
1
1
7–43