DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 94
![KIT DEV MAX V 5M570Z](/photos/18/31/183180/dk-dev-5m570zn_sml.jpg)
DK-DEV-5M570ZN
Manufacturer Part Number
DK-DEV-5M570ZN
Description
KIT DEV MAX V 5M570Z
Manufacturer
Altera
Series
MAX® Vr
Type
CPLDr
Datasheets
1.DK-DEV-5M570ZN.pdf
(30 pages)
2.DK-DEV-5M570ZN.pdf
(2 pages)
3.DK-DEV-5M570ZN.pdf
(30 pages)
4.DK-DEV-5M570ZN.pdf
(164 pages)
5.DK-DEV-5M570ZN.pdf
(24 pages)
Specifications of DK-DEV-5M570ZN
Contents
Board, Cable(s), Software and Documentation
Silicon Manufacturer
Altera
Core Architecture
CPLD
Core Sub-architecture
MAX
Silicon Core Number
5M
Silicon Family Name
MAX V
Kit Contents
MAX V CPLD Development Board, USB Cable
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
5M570ZF256
Lead Free Status / Rohs Status
Compliant
Other names
544-2722
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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5–8
Power-Up Sequencing
Document Revision History
Table 5–4. Document Revision History
MAX V Device Handbook
December 2010
Date
1
Version
For signals with a duty cycle greater than 30% on MAX V input pins, Altera
recommends using a V
signals with a duty cycle less than 30%, the V
MAX V devices are designed to operate in multi-voltage environments where it may
be difficult to control power sequencing. Therefore, MAX V devices are designed to
tolerate any possible power-up sequence. Either V
power to the device and 3.3-, 2.5-, 1.8-, 1.5-, or 1.2-V input signals can drive the
devices without special precautions before V
can operate with a V
When V
device, a delay between V
occur until both power supplies are in their recommended operating range. When
V
connected to V
Thus, any transition on TCK can cause the state machine to transition to an unknown
JTAG state, leading to incorrect operation when V
disable the JTAG state during the power-up sequence, pull TCK low to ensure that an
inadvertent rising edge does not occur on TCK.
Table 5–4
1.0
CCINT
Initial release.
is powered-up, the IEEE Std. 1149.1 JTAG circuitry is active. If TMS and TCK are
CCIO
lists the revision history for this chapter.
and V
CCIO
CCINT
and V
CCIO
CCIO
are supplied from different power sources to a MAX V
voltage level that is higher than the V
CCIO
CCIO
voltage of 3.0 V to guarantee long-term I/O reliability. For
is not powered-up, the JTAG signals are left floating.
and V
CCINT
Chapter 5: Using MAX V Devices in Multi-Voltage Systems
Changes
may occur. Normal operation does not
CCINT
CCIO
voltage can be 3.3 V.
CCIO
or V
CCINT
CCIO
is finally powered-up. To
or V
is applied. MAX V devices
December 2010 Altera Corporation
CCIO
CCINT
can initially supply
level.
Power-Up Sequencing
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