DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 149
![KIT DEV MAX V 5M570Z](/photos/18/31/183180/dk-dev-5m570zn_sml.jpg)
DK-DEV-5M570ZN
Manufacturer Part Number
DK-DEV-5M570ZN
Description
KIT DEV MAX V 5M570Z
Manufacturer
Altera
Series
MAX® Vr
Type
CPLDr
Datasheets
1.DK-DEV-5M570ZN.pdf
(30 pages)
2.DK-DEV-5M570ZN.pdf
(2 pages)
3.DK-DEV-5M570ZN.pdf
(30 pages)
4.DK-DEV-5M570ZN.pdf
(164 pages)
5.DK-DEV-5M570ZN.pdf
(24 pages)
Specifications of DK-DEV-5M570ZN
Contents
Board, Cable(s), Software and Documentation
Silicon Manufacturer
Altera
Core Architecture
CPLD
Core Sub-architecture
MAX
Silicon Core Number
5M
Silicon Family Name
MAX V
Kit Contents
MAX V CPLD Development Board, USB Cable
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
5M570ZF256
Lead Free Status / Rohs Status
Compliant
Other names
544-2722
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices
IEEE Std. 1149.1 Boundary-Scan Register
Figure 8–2. IEEE Std. 1149.1 Circuitry
IEEE Std. 1149.1 Boundary-Scan Register
December 2010 Altera Corporation
Note to
(1) For the boundary-scan register length in MAX V devices, refer to the
TMS
TCK
Figure
TDI
8–2:
Controller
TAP
Figure 8–2
The TAP controller controls the IEEE Std. 1149.1 boundary-scan testing, as described
in
operate the TAP controller and the TDI and TDO pins provide the serial path for the
data registers. The TDI pin also provides data to the instruction register, which then
generates the control logic for the data registers.
The boundary-scan register is a large serial shift register that uses the TDI pin as an
input and the TDO pin as an output. The boundary-scan register consists of 3-bit
peripheral elements that are associated with the I/O pins of the MAX V devices. You
can use the boundary-scan register to test the external pin connections or to capture
internal data.
“IEEE Std. 1149.1 BST Operation Control” on page
UPDATEDR
UPDATEIR
CLOCKDR
CLOCKIR
SHIFTDR
SHIFTIR
shows a functional model of the IEEE Std. 1149.1 circuitry.
Data Registers
Instruction Register
Bypass Register
Boundary-Scan Register (1)
Device ID Register
ISP Registers
Instruction Decode
a
JTAG and In-System Programmability in MAX V Devices
8–6. The TMS and TCK pins
MAX V Device Handbook
chapter.
TDO
8–3
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