DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 38

• Manufacturer Part Number: DK-DEV-5M570ZN
• Description: KIT DEV MAX V 5M570Z
• Manufacturer: Altera
• Series: MAX® Vr
• Type: CPLDr

Specifications of DK-DEV-5M570ZN

• Contents: Board, Cable(s), Software and Documentation
• Silicon Manufacturer: Altera
• Core Architecture: CPLD
• Core Sub-architecture: MAX
• Silicon Core Number: 5M
• Silicon Family Name: MAX V
• Kit Contents: MAX V CPLD Development Board, USB Cable
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: 5M570ZF256
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2722

2–26
I/O Structure
MAX V Device Handbook
IOEs support many features, including:
■
■
■
■
■
■
■
■
■
■
■
■
■
■
MAX V device IOEs contain a bidirectional I/O buffer.
IOE structure. Registers from adjacent LABs can drive to or be driven from the IOE’s
bidirectional I/O buffers. The Quartus II software automatically attempts to place
registers in the adjacent LAB with fast I/O connection to achieve the fastest possible
clock-to-output and registered output enable timing. When the fast input registers
option is enabled, the Quartus II software automatically routes the register to
guarantee zero hold time. You can set timing assignments in the Quartus II software
to achieve desired I/O timing.
LVTTL, LVCMOS, LVDS, and RSDS I/O standards
3.3-V, 32-bit, 33-MHz PCI compliance
JTAG boundary-scan test (BST) support
Programmable drive strength control
Weak pull-up resistors during power-up and in system programming
Slew-rate control
Tri-state buffers with individual output enable control
Bus-hold circuitry
Programmable pull-up resistors in user mode
Unique output enable per pin
Open-drain outputs
Schmitt trigger inputs
Fast I/O connection
Programmable input delay
Figure 2–19
December 2010 Altera Corporation
Chapter 2: MAX V Architecture
shows the MAX V
I/O Structure