DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 40

• Manufacturer Part Number: DK-DEV-5M570ZN
• Description: KIT DEV MAX V 5M570Z
• Manufacturer: Altera
• Series: MAX® Vr
• Type: CPLDr

Specifications of DK-DEV-5M570ZN

• Contents: Board, Cable(s), Software and Documentation
• Silicon Manufacturer: Altera
• Core Architecture: CPLD
• Core Sub-architecture: MAX
• Silicon Core Number: 5M
• Silicon Family Name: MAX V
• Kit Contents: MAX V CPLD Development Board, USB Cable
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: 5M570ZF256
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2722

2–28
MAX V Device Handbook
I/O Blocks
1
The IOEs are located in I/O blocks around the periphery of the MAX V device. There
are up to seven IOEs per row I/O block and up to four IOEs per column I/O block.
Each column or row I/O block interfaces with its adjacent LAB and MultiTrack
interconnect to distribute signals throughout the device. The row I/O blocks drive
row, column, or DirectLink interconnects. The column I/O blocks drive column
interconnects.
5M40Z, 5M80Z, 5M160Z, and 5M240Z devices have a maximum of five IOEs per row
I/O block.
Figure 2–20
Figure 2–20. Row I/O Block Connection to the Interconnect
Note to
(1) Each of the seven IOEs in the row I/O block can have one data_out or fast_out output, one OE output, and
one data_in input.
Figure
LAB Local
Interconnect
2–20:
shows how a row I/O block connects to the logic array.
R4 Interconnects
to Adjacent LAB
Interconnect
Direct Link
LAB
from Adjacent LAB
Interconnect
C4 Interconnects
Direct Link
data_in[6..0]
LAB Column
clock [3..0]
I/O Block Local
Interconnect
(Note 1)
December 2010 Altera Corporation
data_out
fast_out
7
7
7
7
[6..0]
[6..0]
[6..0]
OE
Chapter 2: MAX V Architecture
Row I/O Block
Contains up to
I/O Block
Seven IOEs
Row
I/O Structure