DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 35

• Manufacturer Part Number: DK-DEV-5M570ZN
• Description: KIT DEV MAX V 5M570Z
• Manufacturer: Altera
• Series: MAX® Vr
• Type: CPLDr

Specifications of DK-DEV-5M570ZN

• Contents: Board, Cable(s), Software and Documentation
• Silicon Manufacturer: Altera
• Core Architecture: CPLD
• Core Sub-architecture: MAX
• Silicon Core Number: 5M
• Silicon Family Name: MAX V
• Kit Contents: MAX V CPLD Development Board, USB Cable
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: 5M570ZF256
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2722

Chapter 2: MAX V Architecture
User Flash Memory Block
December 2010 Altera Corporation
Program, Erase, and Busy Signals
Auto-Increment Addressing
Serial Interface
f
f
The UFM block’s dedicated circuitry automatically generates the necessary internal
program and erase algorithm after the PROGRAM or ERASE input signals have been
asserted. The PROGRAM or ERASE signal must be asserted until the busy signal deasserts,
indicating the UFM internal program or erase operation has completed. The UFM
block also supports JTAG as the interface for programming and reading.
For more information about programming and erasing the UFM block, refer to the
User Flash Memory in MAX V Devices
The UFM block supports standard read or stream read operations. The stream read is
supported with an auto-increment address feature. Deasserting the ARSHIFT signal
while clocking the ARCLK signal increments the address register value to read
consecutive locations from the UFM array.
The UFM block supports a serial interface with serial address and data signals. The
internal shift registers within the UFM block for address and data are 9 bits and 16 bits
wide, respectively. The Quartus II software automatically generates interface logic in
LEs for a parallel address and data interface to the UFM block. Other standard
protocol interfaces such as SPI are also automatically generated in LE logic by the
Quartus II software.
For more information about the UFM interface signals and the Quartus II LE-based
alternate interfaces, refer to the
User Flash Memory in MAX V Devices
chapter.
MAX V Device Handbook
chapter.
2–23