ATMEGA168PA-PU Atmel, ATMEGA168PA-PU Datasheet - Page 140
ATMEGA168PA-PU
Manufacturer Part Number
ATMEGA168PA-PU
Description
MCU, 8BIT, AVR, 16K FLASH, 28PDIP
Manufacturer
Atmel
Datasheet
1.ATMEGA48A-PU.pdf
(566 pages)
Specifications of ATMEGA168PA-PU
Controller Family/series
Atmega
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
20MHz
No.
RoHS Compliant
Core Size
8bit
Program Memory Size
16KB
Oscillator Type
External, Internal
Rohs Compliant
Yes
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Manufacturer:
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15.11.8
15.11.9
8271C–AVR–08/10
TIMSK1 – Timer/Counter1 Interrupt Mask Register
TIFR1 – Timer/Counter1 Interrupt Flag Register
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers.
• Bit 7, 6 – Reserved
These bits are unused bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P, and will
always read as zero.
• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector (see “Interrupts” on page 58) is executed when the ICF1 Flag, located in TIFR1, is set.
• Bit 4, 3 – Reserved
These bits are unused bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P, and will
always read as zero.
• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 58) is executed when the OCF1B Flag, located in
TIFR1, is set.
• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 58) is executed when the OCF1A Flag, located in
TIFR1, is set.
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector
(See
• Bit 7, 6 – Reserved
These bits are unused bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P, and will
always read as zero.
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
Bit
(0x6F)
Read/Write
Initial Value
Bit
0x16 (0x36)
Read/Write
Initial Value
”Interrupts” on page
See Section “15.3” on page 116.
R
R
7
–
0
7
–
0
58) is executed when the TOV1 Flag, located in TIFR1, is set.
R
R
6
–
0
6
–
0
ICIE1
R/W
ICF1
R/W
5
0
5
0
R
4
–
0
R
4
–
0
R
3
–
0
R
3
–
0
OCIE1B
OCF1B
R/W
R/W
2
0
2
0
OCIE1A
OCF1A
R/W
R/W
1
0
1
0
TOIE1
TOV1
R/W
R/W
0
0
0
0
TIMSK1
TIFR1
140
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