MB95F126JBPFR-GE1 Fujitsu, MB95F126JBPFR-GE1 Datasheet - Page 56

MCU, 8-BIT, 8FX, 32K FLASH, QFP100

MB95F126JBPFR-GE1

Manufacturer Part Number
MB95F126JBPFR-GE1
Description
MCU, 8-BIT, 8FX, 32K FLASH, QFP100
Manufacturer
Fujitsu
Datasheet

Specifications of MB95F126JBPFR-GE1

Controller Family/series
F2MC-8FX
No. Of I/o's
87
Ram Memory Size
1KB
Cpu Speed
16.25MHz
No. Of Timers
7
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
32KB
Oscillator Type
External Only
MB95120MB Series
56
Sampling at the falling edge of sampling clock*
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for t
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
Serial clock cycle time
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
SCK ↑ → valid SIN hold time
SOT → SCK ↑ delay time
serial clock.
SCK
SOT
SIN
Parameter
2.4 V
0.8 V
0.8 V
0.2 V
Sym-
t
t
t
t
t
SOVHI
bol
SLOVI
SCYC
IVSHI
SHIXI
t
CC
CC
SOVHI
t
IVSHI
SCK, SOT
SCK, SOT
Pin name
SCK, SIN
SCK, SIN
SCK
(V
CC
1
and enabled serial clock delay*
2.4 V
MCLK
= 5.0 V ± 10%, AV
operating output pin :
C
L
.
= 80 pF + 1 TTL.
Internal clock
Condition
t
SHIXI
0.8 V
0.8 V
0.2 V
t
SCYC
SS
CC
CC
= V
t
SLOVI
t
2.4 V
0.8 V
SS
MCLK
5 t
= 0.0 V, T
Min
−95
*
MCLK
3
0
+ 190
*
2
2.4 V
3
Value
A
= −40 °C to + 105 °C)
4 t
Max
+95
MCLK
DS07-12610-5E
*
3
Unit
ns
ns
ns
ns
ns

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