IPR-PCI/MT64 Altera, IPR-PCI/MT64 Datasheet - Page 118
IPR-PCI/MT64
Manufacturer Part Number
IPR-PCI/MT64
Description
IP CORE Renewal Of IP-PCI/MT64
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCI/MT64
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Compiler, Master/Target, 64 bit
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Target Mode Operation
Target Mode
Operation
3–44
PCI Compiler User Guide
clk
rstn
gntn
reqn
ad[63..0]
cben[7..0]
par
par64
idsel
framen
req64n
irdyn
devseln
ack64n
Table 3–34. PCI MegaCore Function Signals (Part 1 of 3)
Signal Name
pci_mt64
Maximum Latency Register
The maximum latency register is an 8-bit read-only register that defines
the frequency in which the function would like to gain access to the PCI
bus. Refer to
This section describes all supported target transactions for the PCI
MegaCore functions. Although this section includes waveform diagrams
showing typical PCI cycles in target mode for the pci_mt64 MegaCore
function, these waveforms are also applicable for the pci_mt32,
pci_t64, and pci_t32 MegaCore functions. The pci_mt64 and
pci_t64 MegaCore functions support both 32-bit and 64-bit
transactions.
each PCI function.
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Table 3–33. Maximum Latency Register Format
Data Bit
7..0
PCI Compiler Version 10.1
Table
Table 3–34
PCI Signals
3–33. You can set this register through the wizard.
pci_t64
Mnemonic
max_lat
v
v
v
v
v
v
v
v
v
v
v
v
lists the PCI and local side signals that apply for
ad[31..0]
cben[3..0]
Read/Write
Read
pci_mt32
v
v
v
v
v
v
v
v
v
Maximum latency register
ad[31..0]
cben[3..0]
Altera Corporation
Definition
January 2011
pci_t32
v
v
v
v
v
v
v
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