IPR-PCI/MT64 Altera, IPR-PCI/MT64 Datasheet - Page 219
IPR-PCI/MT64
Manufacturer Part Number
IPR-PCI/MT64
Description
IP CORE Renewal Of IP-PCI/MT64
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCI/MT64
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Compiler, Master/Target, 64 bit
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Altera Corporation
January 2011
cfg_rd
The cfg_rd command performs single-cycle PCI configuration read
transactions with the address provided in the command argument.
cfg_wr
The cfg_wr command performs single-cycle PCI configuration write
transactions with the address, data, and byte enable provided in the
command arguments.
mem_wr_32
The mem_wr_32 command performs a memory write with the address
and data provided in the command arguments. This command can
perform a single-cycle or burst 32-bit memory write depending on the
number of DWORDs provided in the command argument.
■
Syntax:
Arguments:
Syntax:
Arguments:
The mem_wr_32 command performs a single-cycle 32-bit memory
write if the DWORD value is 1.
PCI Compiler Version 10.1
cfg_rd(address)
address
cfg_wr(address, data, byte_enable)
address
data
byte_enable
Transaction address. This value must be in
hexadecimal radix.
Transaction address. This value must be in
hexadecimal radix.
Transaction data. The data must be in
hexadecimal radix.
Transaction byte enable. The byte enable
value must be in hexadecimal radix
PCI Compiler User Guide
Testbench
4–9
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