IPR-PCI/MT64 Altera, IPR-PCI/MT64 Datasheet - Page 203
IPR-PCI/MT64
Manufacturer Part Number
IPR-PCI/MT64
Description
IP CORE Renewal Of IP-PCI/MT64
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCI/MT64
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Compiler, Master/Target, 64 bit
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Altera Corporation
January 2011
PCI Configuration Write Transaction from the pci_mt64 Local Master
Device to the Internal Configuration Space
Figure 3–47
configuration write transaction to internal configuration space. The local
master requests a 32-bit transaction by asserting the lm_req32n signal.
When requesting a configuration write transaction, the pci_mt64
function will automatically perform a single-cycle transaction. The local
master signals are asserted as if the pci_mt64 master is completing a
single-cycle 32-bit memory write transaction, similar to
Master Mode Operation section. The pci_mt64 function’s internal
configuration space will respond to the transaction without affecting the
local side signals.
pci_mt32 MegaCore functions, excluding the 64-bit extension signals as
noted for pci_mt32.
PCI Compiler Version 10.1
shows the behavior of the pci_mt64 master performing a
Figure 3–47
applies to both the pci_mt64 and
Functional Description
Figure 3–43
in the
3–129
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