IPR-PCI/MT64 Altera, IPR-PCI/MT64 Datasheet - Page 179
IPR-PCI/MT64
Manufacturer Part Number
IPR-PCI/MT64
Description
IP CORE Renewal Of IP-PCI/MT64
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCI/MT64
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Compiler, Master/Target, 64 bit
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Figure 3–36. 32-Bit PCI & 32-Bit Local-Side Single-Cycle Memory Read Master Transaction
Note to
(1)
Altera Corporation
January 2011
This signal is not applicable to the pci_mt32 MegaCore function.
Figure
(1) l_dato[63..32]
(1) l_cbeni[7..4]
(1) l_hdat_ackn
(1) l_ldat_ackn
lm_adr_ackn
l_cbeni[3..0]
l_dato[31..0]
l_adi[31..0]
lm_tsr[9..0]
3–36:
(1) ack64n
lm_req32n
(1) req64n
cben[3..0]
ad[31..0]
lm_dxfrn
lm_lastn
lm_ackn
lm_rdyn
devseln
framen
stopn
trdyn
irdyn
reqn
gntn
par
clk
1
000
Figure 3–36
The transaction shown in
Figure
requests a 32-bit transaction by asserting lm_req32n. This figure applies
to both the pci_mt64 and pci_mt32 MegaCore functions, excluding the
64-bit extension signals as noted for pci_mt32.
2
3–35, except that in
3
PCI Compiler Version 10.1
001
shows a 32-bit single cycle memory read master transaction.
4
5
002
Adr
0
0
Figure 3–36
6
Figure 3–36
6
Adr
004
BE_L
6
7
Adr-PAR
is the same as shown in
the local side master interface
Z
BE_L
8
008
D0_L
Z
9
D0-L-PAR
Functional Description
D0_L
108
Z
10
Z
000
3–105
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