IPR-PCI/MT64 Altera, IPR-PCI/MT64 Datasheet - Page 175
IPR-PCI/MT64
Manufacturer Part Number
IPR-PCI/MT64
Description
IP CORE Renewal Of IP-PCI/MT64
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCI/MT64
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Compiler, Master/Target, 64 bit
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Altera Corporation
January 2011
The local side deasserts lm_rdyn in clock cycle 9. Consequently, on the
following clock cycle (clock cycle 10), the pci_mt64 function suspends
data transfer on the local side by deasserting the lm_dxfrn signal and on
the PCI side by deasserting the irdyn signal.
Figures 3–34
bus target inserting a wait state. This figure applies to both pci_mt64
and pci_mt32 MegaCore functions, excluding the 64-bit extension
signals as noted for pci_mt32. The PCI side inserts a wait state by
deasserting trdyn in clock cycle 9. Consequently, on the following clock
cycle (clock cycle 10), the function deasserts the lm_ackn and lm_dxfrn
signal on the local side. Data transfer is suspended on the PCI side in
clock cycle 9 and on the local side in clock cycle 10.
PCI Compiler Version 10.1
shows the same transaction as in
Figure 3–31
Functional Description
with the PCI
3–101
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