IPR-PCI/MT64 Altera, IPR-PCI/MT64 Datasheet - Page 132
IPR-PCI/MT64
Manufacturer Part Number
IPR-PCI/MT64
Description
IP CORE Renewal Of IP-PCI/MT64
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCI/MT64
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Compiler, Master/Target, 64 bit
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Target Mode Operation
Figure 3–11. 32-Bit PCI and 64-Bit Local-Side Single-Cycle Memory Read Target Transaction
3–58
PCI Compiler User Guide
l_adro[31..0]
l_adi[63..32]
l_hdat_ackn
l_cmdo[3..0]
l_beno[7..4]
l_beno[3..0]
l_ldat_ackn
lt_tsr[11..0]
l_adi[31..0]
cben[3..0]
lt_framen
ad[31..0]
devseln
ack64n
lt_dxfrn
framen
req64n
lt_ackn
lt_rdyn
stopn
trdyn
irdyn
par
clk
1
2
Figure 3–11
6. In clock cycle 7, the pci_mt64 and pci_t64 functions drive the least
significant DWORD on ad[31..0]. The pci_mt64 and pci_t64
functions drive the correct parity value on the par signal in clock cycle 8.
1
000
Adr
6
3
The pci_mt64 and the pci_t64 functions always transfer
64-bit data on the local side. In a 32-bit single-cycle memory read
transaction, only one DWORD is transferred to the PCI master.
Adr-PAR
PCI Compiler Version 10.1
shows that the local side transfers a full QWORD in clock cycle
4
Z
Z
5
BE0_L
6
101
D0_H
D0_L
Adr
6
BE0_H
BE0_H
BE0_L
BE0_L
7
D0_L
8
D0-L-PAR
501
9
Altera Corporation
000
January 2011
10
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