IPR-PCI/MT64 Altera, IPR-PCI/MT64 Datasheet - Page 48
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
IPR-PCI/MT64
Manufacturer Part Number
IPR-PCI/MT64
Description
IP CORE Renewal Of IP-PCI/MT64
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCI/MT64
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Compiler, Master/Target, 64 bit
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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The Quartus II Simulation Files
1–14
PCI Compiler User Guide
mmbr
mmsr
mmbr_mabrt
mmbr_tabrt
mmbr_tdisc_wd
mmbr_tdisc_wod
mmbr_tret
mmbr_lte
mior
mcfgr
mmbw
mmsw
mmbw_mabrt
mmbw_tabrt
mmbw_tdisc_wd
mmbw_tdisc_wod
mmbw_tret
mmbw_lte
miow
mcfgw
Table 1–3. pci_mt32 Master Simulation Files
Simulation File
Name
Memory Burst Read
Memory Single-Cycle
Master Abort
Target Abort Response
Target Disconnect with Data Response
Target Disconnect without Data Response
Target Retry Response
Latency Timer Expires
I/O Read
Configuration Read
Memory Burst Write
Memory Single-Cycle
Master Abort
Target Abort Response
Target Disconnect with Data Response
Target Disconnect without Data Response
Target Retry Response
Latency Timer Expires
I/O Write
Configuration Write
Table 1–3
<path>\pci_compiler\megawizard_flow\qexamples\
pci_mt32\sim\master directory.
describes the Quartus II simulation files included in the
PCI Compiler Version 10.1
Master Write
Master Read
Description
Altera Corporation
January 2011
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