IPR-PCI/MT64 Altera, IPR-PCI/MT64 Datasheet - Page 285
IPR-PCI/MT64
Manufacturer Part Number
IPR-PCI/MT64
Description
IP CORE Renewal Of IP-PCI/MT64
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCI/MT64
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Compiler, Master/Target, 64 bit
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
- Current page: 285 of 358
- Download datasheet (3Mb)
Figure 7–7. PCI Target-to-Avalon-MM Master Block Diagram
Altera Corporation
January 2011
MegaCore
Function
PCI
Controller
Target
PCI
■
■
Figure 7–7
Avalon-MM master ports.
Non-Prefetchable Operations
Non-prefetchable operations are defined as either transactions that hit:
■
■
As previously noted, PCI write operations involve only one PCI
transaction where the address/command and data is transferred. The
read operation involves at least two PCI transactions. In the first PCI
transaction (request), the address and data are transferred to the
PCI-Avalon bridge, and in the second transaction (completion), the
PCI-Avalon bridge transfers the data.
Non-Prefetchable
Non-Prefetchable
Read requests will always be initially retried and completed as
delayed read operations.
The requests will be directed to the prefetchable Avalon-MM master
port. The data path between the PCI bus and this Avalon-MM port
will be optimized to support higher bandwidth that results in higher
latency to transition through the required RAM buffers.
A non-prefetchable BAR
A prefetchable BAR if the Single-Cycle Transfers Only target
performance profile is used
Prefetchable
Addr/Data
Write Data
Address
PCI Compiler Version 10.1
shows the bridge logic between the PCI target controller and
Read Response Register
Response Data Buffer
Write Data Register
Prefetchable Read
Command Register
Non-Prefetchable
Non-Prefetchable
Non-Prefetchable
Command/Write
Prefetchable
Data Buffer
Read Data
Read Data
Prefetchable
Avalon Master Port
Non-Prefetchable
Avalon Master Port
Write Data
Address
Write Data
Address
Functional Description
7–17
Related parts for IPR-PCI/MT64
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
IP CORE Renewal Of IP-PCI/MT32
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/T32
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/T64
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCIE/1
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCIE/4
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCIE/8
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet: