IPR-QDRII/UNI Altera, IPR-QDRII/UNI Datasheet - Page 29

• Manufacturer Part Number: IPR-QDRII/UNI
• Description: IP CORE Renewal Of IP-QDRII/UNI
• Manufacturer: Altera

Specifications of IPR-QDRII/UNI

• Software Application: IP CORE, Memory Controllers, SRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

General Settings
December 2010 Altera Corporation
Clocks
Advanced PHY Settings
This chapter describes the QDR II and QDR II+ SRAM Controller with UniPHY IP
core parameters that you can set in the GUI.
The General Settings tab allows you to configure the following parameter settings.
Table 3–1
Table 3–1. Clock Settings
Table 3–2
Table 3–2. Advanced PHY Settings
Memory clock frequency
PLL reference clock frequency
Full or half rate on Avalon-MM
interface
Additional address/command clock
phase
Generate power-of-2 bus widths
Maximum Avalon-MM burst length
I/O standard
Master for PLL/DLL sharing
describes the clock settings.
describes the advanced PHY settings.
Parameter
Parameter
Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide
The frequency of the clock that drives the memory device.
The frequency of the clock that feeds the PLL.
Defines the width of the data bus on the Avalon-MM
interface. A setting of Full results in a width twice the
memory data width. A setting of Half results in a width of
four times the memory data width.
Increases or decreases the phase shift of the
address/command clock. The base phase shift center-
aligns the address/command clock at the memory device.
In some circumstances, you can improve timing by
increasing or decreasing the phase shift.
Rounds down the Avalon-MM side data bus to the nearest
power of 2.
Specifies the maximum burst length on the Avalon-MM
bus.
Specifies the I/O standard voltage.
Causes UniPHY to instantiate its own PLL and DLL. All of
the PLL clocks and DLL delay values are exported for use
by other identical UniPHY cores that have this option
turned on.
3. Parameter Settings
External Memory Interface Handbook Volume 3
Description
Description