IPR-QDRII/UNI Altera, IPR-QDRII/UNI Datasheet - Page 30
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IPR-QDRII/UNI
Manufacturer Part Number
IPR-QDRII/UNI
Description
IP CORE Renewal Of IP-QDRII/UNI
Manufacturer
Altera
Datasheet
1.IP-QDRIIUNI.pdf
(74 pages)
Specifications of IPR-QDRII/UNI
Software Application
IP CORE, Memory Controllers, SRAM
Supported Families
Arria II GX, HardCopy III, Stratix III, Stratix IV
Core Architecture
FPGA
Core Sub-architecture
Arria, HardCopy, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
3–2
Memory Parameters
External Memory Interface Handbook Volume 3
Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide
Topology
Controller Settings
Table 3–2. Advanced PHY Settings
Table 3–3
Table 3–3. Topology Settings
Table 3–4
Table 3–4. Controller Settings
The Memory Parameters tab allows you to configure memory device parameters. You
can enter parameters manually from the manufacturer’s device data sheet, or you can
populate the fields automatically by selecting the required device from the list of
presets.
Table 3–5
Table 3–5. Memory Parameters (Part 1 of 2)
Master for OCT control block
Hardcopy compatibility mode
Example Testbench Simulation options
Skip memory initialization
Device width
Device depth
Controller latency
Address width
Data width
describes the topology settings.
describes the controller settings.
describes the memory parameters.
Parameter
Parameter
Parameter
Parameter
Causes UniPHY to instantiate the required OCT control
block. When this parameter is turned off, you must
instantiate this block and connect the termination control
bus signals to the PHY, or share an OCT control block from
another UniPHY instantiation that is in master mode.
Causes the generated UniPHY memory interface to have all
required HardCopy compatibility options enabled. For
example, PLLs and DLLs will have their reconfiguration
ports exposed.
Causes the example testbench to skip the memory
initialization sequence. This setting does not change the
generated RTL, but can speed up simulation.
Specifies the number of devices used for width expansion.
Specifies the number of devices (ranks) used for depth
expansion.
Specifies the number of clock cycles required for a request
to pass through an idling controller.
The width of the address bus on the memory device.
The width of the data bus on the memory device.
Description
Description
Description
Description
December 2010 Altera Corporation
Chapter 3: Parameter Settings
Memory Parameters