IPR-QDRII/UNI Altera, IPR-QDRII/UNI Datasheet - Page 54

• Manufacturer Part Number: IPR-QDRII/UNI
• Description: IP CORE Renewal Of IP-QDRII/UNI
• Manufacturer: Altera

Specifications of IPR-QDRII/UNI

• Software Application: IP CORE, Memory Controllers, SRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–14
Table 6–8. Parameters (Part 2 of 2)
External Memory Interface Handbook Volume 3
Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide
Parameter Name
AFI_CONTROL_WIDTH
AFI_DATA_WIDTH
AFI_DQS_WIDTH
DLL_DELAY_CTRL_WIDTH
NUM_SUBGROUP_PER_READ_DQS
QVLD_EXTRA_FLOP_STAGES
READ_VALID_TIMEOUT_
WIDTH
READ_VALID_FIFO_WRITE_ADDR
_WIDTH
READ_VALID_FIFO_READ_
ADDR_WIDTH
MAX_LATENCY_COUNT_
WIDTH
MAX_READ_LATENCY
READ_FIFO_READ_ADDR_
WIDTH
READ_FIFO_WRITE_ADDR_
WIDTH
MAX_WRITE_LATENCY_
COUNT_WIDTH
INIT_COUNT_WIDTH
SEQ_BURST_COUNT_WIDTH
VCALIB_COUNT_WIDTH
DOUBLE_MEM_DQ_WIDTH
HALF_AFI_DATA_WIDTH
CALIB_REG_WIDTH
NUM_AFI_RESET
AFI Signal Names
The QDR II and QDR II+ SRAM controllers with UniPHY use AFI.
The AFI timing is identical to the DDR3 SDRAM AFI in the Quartus II software
version 9.0. However, some signals have been renamed, some added, and others
removed from the AFI definition. The AFI includes only signals that are part of the
controller-to-PHY interface, clocks, and reset. All signals on the controller-to-PHY
interface have the afi_ prefix to the signal name.
signals and original (Quartus II software version 9.0) names.
Table 6–9. AFI New Signal Names
afi_clk
afi_reset_n
Description
The AFI control width, derived from the corresponding memory interface width.
The AFI data width.
The AFI DQS width.
The DLL delay output control width.
A read datapath parameter for timing purposes.
A read datapath parameter for timing purposes.
A read datapath parameter; calibration fails when the timeout counter expires.
A read datapath parameter; the write address width for half-rate clocks.
A read datapath parameter; the read address width for full-rate clocks.
A latency calibration parameter; the maximum latency count width.
A latency calibration parameter; the maximum read latency.
—
—
A write datapath parameter; the maximum write latency count width.
An initailization sequence.
The burst count width for the sequencer.
The width of a counter used by the sequencer.
—
—
The width of the calibration status register.
The number of AFI resets to generate.
AFI Name
ctl_clk
ctl_reset_n
Table 6–9
Chapter 6: Functional Description—UniPHY
shows the renamed AFI
December 2010 Altera Corporation
Old Name
UniPHY Signals