IPR-QDRII/UNI Altera, IPR-QDRII/UNI Datasheet - Page 49

• Manufacturer Part Number: IPR-QDRII/UNI
• Description: IP CORE Renewal Of IP-QDRII/UNI
• Manufacturer: Altera

Specifications of IPR-QDRII/UNI

• Software Application: IP CORE, Memory Controllers, SRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Functional Description—UniPHY
Interfaces
December 2010 Altera Corporation
The OCT Sharing Interface
1
By default, the UniPHY IP generates the required OCT control block in the top-level
RTL file for the PHY. If you want, you can instantiate this block elsewhere in your
code and feed the required termination control signals into the IP core by turning off
Master for OCT Control Block on the PHY Settings tab. If you turn off Master for
OCT Control Block, you must instantiate the OCT control block, or use another
UniPHY instance as a master, and ensure that the parallel and series termination
control bus signals are connected to the PHY.
Termination Control Block assignments must be created for all calibrated input-only
pins, to designate which OCT control block to use for those pins. If the UniPHY IP is
in OCT Control Block master mode, these assignments are included in the
<variation_name>_pin_assignments.tcl file which must be run after analysis and
synthesis. If the UniPHY IP is not using OCT Control Block master mode you must
manually create the required assignments to connect the input-only pins to the
relevant OCT control block. For QDRII this is the input clocks and input data pins, all
output and bidirectional pins are hard coded between the pin's I/O buffer and the
series and parallel termination control signals.
Figure 6–6
Master for OCT Control Block.
Figure 6–6. PHY Architecture with Master for OCT Control Block
Figure 6–7. PHY Architecture without Master for OCT Control Block
The OCT Sharing Interface and OCT slave mode are not available with SOPC Builder.
Memory Interface
RUP and RDN
Memory Interface
RUP and RDN
and
Figure
OCT
6–7, respectively, show the PHY architecture with and without
OCT
Series and Parallel
Termination Control
Buses
OCT
Sharing
Interface
Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide
UniPHY Top-Level File
UniPHY Top-Level File
PLL and DLL Sharing Interface
Sharing Interface
DLL
PLL and DLL
DLL
UniPHY
UniPHY
PLL
PLL
External Memory Interface Handbook Volume 3
Reset Interface
Reset Interface
AFI
AFI
6–9