IPR-QDRII/UNI Altera, IPR-QDRII/UNI Datasheet - Page 50

• Manufacturer Part Number: IPR-QDRII/UNI
• Description: IP CORE Renewal Of IP-QDRII/UNI
• Manufacturer: Altera

Specifications of IPR-QDRII/UNI

• Software Application: IP CORE, Memory Controllers, SRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–10
UniPHY Signals
Table 6–4. Clock and Reset Signals
Table 6–5. AFI Signals (Part 1 of 2)
External Memory Interface Handbook Volume 3
Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide
pll_ref_clk
global_reset_n
soft_reset_n
reset_request_n
seriesterminationcontrol
parallelterminationcontrol
oct_rdn
oct_rup
Clocks and Reset
afi_clk
afi_reset_n
Name
Name
This section describes the UniPHY signals.
signals.
Table 6–5
shows the AFI signals.
Input
Input
Input
Output
Input (for
OCT slave)
Output(for
OCT master)
Input (for
OCT slave)
Output(for
OCT master)
Input (for
OCT master)
Input (for
OCT master)
Output
Output
Direction
Direction
PLL reference clock input.
Active low global reset for PLL and all logic in the PHY, which causes a
complete reset of the whole system.
Holding soft_reset_n low holds the PHY in a reset state. However it
does not reset the PLL, which keeps running. It also holds the
afi_reset_n output low. Mainly for use by SOPC Builder.
When the PLL is locked, reset_request_n is high. When the PLL is
out of lock, reset_request_n is low.
Required signal for PHY to provide series termination calibration value.
Must be connected to a user-instantiated OCT control block (alt_oct) or
another UniPHY instance that is set to OCT master mode.
Unconnected PHY signal, available for sharing with another PHY.
Required signal for PHY to provide series termination calibration value.
Must be connected to a user-instantiated OCT control block (alt_oct) or
another UniPHY instance that is set to OCT master mode.
Unconnected PHY signal, available for sharing with another PHY.
Must connect to calibration resistor tied to GND on the appropriate RDN
pin on the device. (See appropriate device handbook.)
Must connect to calibration resistor tied to V
pin on the device. (See appropriate device handbook.)
1
1
Width
Table 6–4
Half-rate or full-rate clock supplied to
controller and system logic.
Reset output on afi_clk clock domain. For
use as asynchronous reset. This signal is
asynchronously asserted and
synchronously deasserted.
Description
Chapter 6: Functional Description—UniPHY
shows the clock and reset
December 2010 Altera Corporation
ccio
Description
on the appropriate RUP
UniPHY Signals