IPR-QDRII/UNI Altera, IPR-QDRII/UNI Datasheet - Page 45

• Manufacturer Part Number: IPR-QDRII/UNI
• Description: IP CORE Renewal Of IP-QDRII/UNI
• Manufacturer: Altera

Specifications of IPR-QDRII/UNI

• Software Application: IP CORE, Memory Controllers, SRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Functional Description—UniPHY
Block Description
Figure 6–4. Read Datapath
Table 6–3. Sequencer States
December 2010 Altera Corporation
State
RESET
LOAD_INIT
STABLE
Q[0...n]
CQn
CQ
PLL
Sequencer
DLL
DQS Delay Chain
ALTDQ_DQS
In half-rate designs, the write side of the FIFO buffer should be double the size of the
read side of the FIFO buffer. The read side only reads one entry after the write side has
written into two entries, which effectively converts data from SDR to HDR. In full-rate
designs, the size of the FIFO buffer is the same for both write and read as both sides
operate at the same rate. For half-rate designs, the FIFO operates at half-rate on both
read and write sides, and contains 4 half-rate entries; for full-rate designs, the FIFO
operates at full-rate on both read and write sides, and contains 8 full-rate entries.
Figure 6–4
(DQ) returned from memory are edge-aligned; the DQS and DQSn delay chains shift
the clocks to achieve center alignment.
The sequencer is a state machine that processes the calibration algorithm. The
sequencer assumes control of the interface at reset (whether at initial startup or when
the IP is reset) and maintains control throughout the calibration process, relinquishing
control to the memory controller only after successful calibration.
major states in the sequencer.
DQSn Delay Chain
Description
Remain in this state until reset is released.
Load any initialization values for simulation purposes.
Wait until the memory device is stable. The QDR II and QDR II+ specification requires 2,048
cycles of power up wait time.
illustrates the read datapath. The DQS and DQSn clocks and the read data
DDIO_IN
DDIO_IN_n-1
Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide
calibrated by PHY
write enable
read_capture_clk
data_high
data_low
External Memory Interface Handbook Volume 3
FIFO
Table 6–3
read valid
pll_afi_clk
shows the
read data
6–5