IPR-QDRII/UNI Altera, IPR-QDRII/UNI Datasheet - Page 58

• Manufacturer Part Number: IPR-QDRII/UNI
• Description: IP CORE Renewal Of IP-QDRII/UNI
• Manufacturer: Altera

Specifications of IPR-QDRII/UNI

• Software Application: IP CORE, Memory Controllers, SRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–18
External Memory Interface Handbook Volume 3
Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide
Figure 6–12
read from the same address. In each example, afi_rdata and afi_wdata are aligned
with controller clock (afi_clk) cycles. All the data in the bit vector is valid at once.
The AFI has the following conventions:
■
■
Figure 6–12
■
■
■
With the AFI, high and low signals are combined in one signal, so for a single
chip-select (afi_cs_n) interface, afi_cs_n[1:0], where location 0 appears on the
memory bus on one mem_clk cycle and location 1 on the next mem_clk cycle.
1
Spaced reads and writes have the following definitions:
■
■
The burst length is four.
An 8-bit interface with one chip-select.
The data for one controller clock (afi_clk) cycle represents data for two memory
clock (mem_clk) cycles (half-rate interface).
Spaced writes—write commands separated by a gap of one controller clock
(afi_clk) cycle.
Spaced reads—read commands separated by a gap of one controller clock
(afi_clk) cycle.
This convention is maintained for all signals, so for an 8 bit memory
interface, the write data (afi_wdata) signal is afi_wdata[31:0], where the
first data on the DQ pins is afi_wdata[7:0], then afi_wdata[15:8], then
afi_wdata[23:16], then afi_wdata[31:24].
and
through
Figure 6–13
Figure 6–13
show writes and reads, where the data is written to and
assume the following general points:
Chapter 6: Functional Description—UniPHY
December 2010 Altera Corporation
PHY-to-Controller Interfaces